Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Questions on Bandgap performance on silicon

Status
Not open for further replies.
S

suria3

Full Member level 5
Joined
Mar 5, 2004
Messages
300
Helped
17
Reputation
34
Reaction score
5
Trophy points
1,298
Activity points
3,028
Hi Guys,

I have a concern on the bandgap design. I have covered the process/voltage/temperature + montecarlo simulations on both the pre layout and post layout simulations, and the result are in the
expected range with typically ~1.2V of the bandgap output voltage. The montecarlo simulations
were performed around 1000 samples run as well, where the min and max sigma deviation also
in the range of 1.15V to 1.25V (extraction simulation), which is the targeted range.

Question is, on the silicon, during the test, will the bandgap result will vary further from what we observed from the simulated range? Will it still vary beyond 1.25V, and less than 1.15V?

Thanks
Suria
 

That would depend on how well the modeling group fitted
the statistics, relative to what the foundry can produce.
Often this is very "sandbagged" and any small sample will
fit well within the span of simulated results (aside from
defect and processing "sports"). This can drive "overdesign"
(like building in trim bits or more of them than really needed)
or overly lax test limits which relieve the fab of any pain
from which to learn (presuming that you and they are such
good friends that your pain is their pain).
 
  • Like
Reactions: suria3

    S

    suria3

    Points: 2
    Helpful Answer Positive Rating
dick_freebird said:
That would depend on how well the modeling group fitted
the statistics, relative to what the foundry can produce.
Often this is very "sandbagged" and any small sample will
fit well within the span of simulated results (aside from
defect and processing "sports"). This can drive "overdesign"
(like building in trim bits or more of them than really needed)
or overly lax test limits which relieve the fab of any pain
from which to learn (presuming that you and they are such
good friends that your pain is their pain).
Click to expand...

I didn't enable any trim bit options in the design, provided that I have covered montecarlo simulation run that gives the output voltage to the targeted range. As you explained, I believe the process model is modeled correctly in the pdk files.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top