How to decide whether we can start doing physical design with a given netlist?

In each stage of the PnR flow, should we try to fix all the violations
or can we proceed even if we have some violation? What is the criteria for
it? For example, when I go for floorplanning, should I make sure that the
initial netlist itself does not have any negative WNS? How much WNS and
TNS I can allow in the initial phase? Should I try to fix all the setup violations in the initial netlist before going to PnR? Or can I expect some of them to be fixed in the PnR stage? How much tolerance I can give to WNS or TNS or set up violations? What about in the successive steps
of physical design flow? Should I try to fix all the timing, congestion and
max transition, max cap violations before i move to placement,CTS,routing
etc.

You needs lots of experience with the technology being used, the tools being used, the constraints being set, as well as good understanding of the design itself. There is no clear cut answer for your question.

I have had designs that had millions of violations after placement, and then those were all fixed at CTS by using useful skew.
I have had designs with -1ps at the start of physical synthesis, and it was never possible to fix it later.

So.. in general, is there any thumb rule we can depend on?? Something like, say a netlist with WNS value less than 5% of the clock period can be used for floorplan? Or a maxcap violation of some value can be left as such in some stage and can be fixed by buffer resizing in the upcoming stages??

I have adopted different rules of thumb for each tech I have worked with, more or less. Specifically for the floorplan stage, I would worry about congestion and access to pins first, power distribution. Focus on what those routing channels are looking like. Then you have to figure out if some of your floorplan decisions made timing completely unfeasible. It is usually safe to start with some form of automated floorplan, and then manually improve it to your liking. DRVs will appear at this point, hundreds, or even thousands. Don't worry yet.

Once you are done with that, it is time for placement. You can play with congestion vs timing effort, depending on what you need the most. Placement will take DRV into account if you do OPT at the same time (in cadence lingo that means running place_opt_design). You might still find some DRV violations after placement, but they should be way less than before. Some max_cap violations can occur, some max_tran, even some max_fanout. I wouldn't try to fix all of them before routing and final OPT, but I would make sure I understand where they are coming from. If you have a block that is buried so deep in the floorplan that every wire connecting to it has max_length violations, there is nothing OPT can do for you.