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Topology and circuit doubt

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CAMALEAO

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Hi everyone,

I am new in this forum and into analogue IC design.

I am trying to analyse the following circuit:

**broken link removed**

But right now what is intriguing me is this bit:

**broken link removed**

Can you check if I have drew correctly where the current goes? (in green and red)

**broken link removed**

If I wanted to simulate separately this part of the circuit:

**broken link removed**

How can I lay down the circuit and adapt it? I did it this way, but I don't know if it is correct:

**broken link removed**

The current source is has to be like a vin source? It has to be a signal source and not a dc current source correct?

That said I would like to make a basic question. From what I can tell M13 e a common source, the M14 is a common drain configuration, right? (source follower).

If it is, let me do a comment. In school we learn that the common gate needs to have it's drain terminal connected to a ground signal, that is, a vdd point.

Now in this circuit we don't have a vdd point in the gate of M15, so how is supposed to be a ground signal and as well provide a bias voltage ou a supply voltage to it?

Regards.
 

Sorry, your attached images expired. This happens occasionally, reason unknown. Possibly because of huge image size?

Try posting images again, using the 'Add an Image' button. It might be a good idea to size your images to fit the average screen.
 

... the M14 is a common drain configuration, right? (source follower).

If it is, let me do a comment. In school we learn that the common gate needs to have it's drain terminal connected to a ground signal, that is, a vdd point.

No, I think that's not correct: a common gate circuit has its input at the source and its output at the drain, i.e. its load between drain and VDD (in case of an nMOS).

Probably you mixed this up with the common drain circuit, which has its drain connected to a ground signal.

I also can't see your attachments, BTW.
 

Hi both. Thanks for the reply.

@erikl, yes you are right, my mistake. It is true, I was thinking correctly but wrote in the wrong way. I meant:

"(...) the common gate needs to have it's gate terminal connected to a ground signal, that is, a vdd point. (...)

Regarding the picture I don't know what happened. I will re-upload them in the shortest time possible.

Thanks.
 

Ok, I can now upload the images. Since I can not edit the post I will re-write it and put the images in place.

Hi everyone,

I am new in this forum and into analogue IC design.

I am trying to analyse the following circuit:

1.png

But right now what is intriguing me is this bit (which is the same for the pmos side):

2.png

Can you check if I have drew correctly where the current goes? (in green and red)

3.png

If I wanted to simulate separately this part of the circuit:

2.png

How can I lay down the circuit and adapt it? I did it this way, but I don't know if it is correct:

4.png

The current source has to be like a vin source? It has to be a signal source and not a dc current source correct? In this case what can we consider the input and the output?

That said I would like to make a basic question. From what I can tell M13 e a common source, the M14 is a common drain configuration, right? (source follower).

If it is, let me do a comment. In school we learn that the common drain needs to have it's drain terminal connected to a ground signal, that is, a vdd point. But in the case of this circuit that I am showing to you guys, we don't have a vdd point in the gate of M15, so how is supposed to be a ground signal and as well provide a bias voltage ou a supply voltage to it?

Thanks in advance.
 

Your first schematic resembles an op amp. The final section applies the correct voltage to the load. Simultaneously it must sink/source the correct amount of current through the load. It's easy to describe but it requires a complicated circuit.

I believe your red-lined sections are for the same purpose, although I'm unable to explain how it does it.
 

Your circuit is sort of a redrawn type of from 1986 *). If you have access to these papers, you can find good explanations therein. I think this overview also gives good explanations: View attachment rail-to-rail_IO-amp.pdf.

In school we learn that the common gate needs to have it's drain terminal connected to a ground signal, that is, a vdd point.

Now in this circuit we don't have a vdd point in the gate of M15, so how is supposed to be a ground signal and as well provide a bias voltage ou a supply voltage to it?

What you have learnt in school is correct, but it refers to signal paths, i.e. small signal consideration. In this biasing circuit, just the DC operation point - current in this case - is relevant. Check the papers above!



*) IEEE paper, mustn't be published in this forum

- - - Updated - - -

...

How can I lay down the circuit and adapt it? I did it this way, but I don't know if it is correct:

View attachment 131139

The current source has to be like a vin source? It has to be a signal source and not a dc current source correct? In this case what can we consider the input and the output?
...

The "is" current sink is just varying Vout (a little bit). This circuit alone doesn't make much sense (to me). Don't think of ac amplifiers, this is only a DC bias source! Such a bias circuit is known as "beta helper", if it is made by two BJTs.

I think it doesn't make much sense to break down this complex bias circuit (your 1st image) into such parts - it has to be considered as the whole bias structure: M14 actually is in parallel to M12, M11 and M13 are part of their bias sources, called floating bias or folded mesh, s. the literature stated above.
 

I see.

So what you mean is that that circuit in the red box is some sort of biasing network? If so, to bias what?
This particular configuration reminds me the regulated cascode topology, where rin is in the order of 1/gm and rout gm^2 * rds^3.

Regarding the signal path, that goes out from the diff. input pair, pass through the cascade branch where we find M8 and then it is applied to M15? So that circuit at its gate (red square) is doing out?
 

I agree with erikl that it doesn't make much sense to break the circuit apart.

Some hints about the circuit function.

In balanced state (Id.M8 = -Id.M9), the marked circuit is part of a current mirror. Presuming equal areas (you should sketch a simulation circuit with actual transistor area factors), M13/M16 and M11/M15 are both acting as current mirrors, biasing the output stage with 20 µA. An input current difference is amplified and transfered to the output.

Suggest to observe the complete behavior in a simulation.
 

FvM, ok. If in the M13-M16 are acting as a current mirror, what is the M14 doing there? We can imagine that if that M14 wasn't there, that M13 would be a diode connected device.
 

... what is the M14 doing there?

M14 is the second transistor of the floating current mirror M12||M14, which are an anti-parallel pair. I think you can see this better in the following PNG on
Monticelli's Class-AB biasing scheme: Here M3||M4 is the floating current mirror. Monticelli_Class-AB_biasing_scheme.png
 
Last edited:

Hi erikl, I can't see the attachment.
 

You're right, it didn't last very long :-( I'll attach it (in my former post) as a PNG image now.
 

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