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Post layout simulation

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marjang

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Hi every one,
I have finished place & route my design by using IC compiler. Now I want to do the simulation with Hspice, but I do not have any idea how can I import the output of IC compiler which is in GDSII format into hspice. Has any one have any idea?
Thank you in advance.
Marjan
 

err, no. you need to extract first, then use the extracted netlist with hspice.

since you have used ICC, I assume this is a decent sized digital design. be aware that hspice simulation might not be feasible.
 

ThisIsNotSam said:
err, no. you need to extract first, then use the extracted netlist with hspice.

since you have used ICC, I assume this is a decent sized digital design. be aware that hspice simulation might not be feasible.
Click to expand...



Thanks for your response.
How can I extract this netlist from IC compiler? can you please help me more with it?
If you think hspice is not good, what else do you suggest?
 

You can do back-annotation simulation using SPEF of SDF plus the netlist which can be exported from ICC.
Then, input them to a simulator VCS, ModelSim ....
 

marjang said:
Thanks for your response.
How can I extract this netlist from IC compiler? can you please help me more with it?
If you think hspice is not good, what else do you suggest?
Click to expand...

what do you want to accomplish exactly?
 

ThisIsNotSam said:
what do you want to accomplish exactly?
Click to expand...

I have a small design which is already placed and routed. I have to do post layout simulation to make sure it is working correctly. My college had done the pre simulation with hspice, thats why I am going to use hspice too.
Now my question is that I can extract the verilog file from IC compiler, but not hspice file. How can I use the output of IC compiler in hspice environment? Is there a tool to convert verilog to hspice?

That would be your kindness helping me.

Thanks in advance.
 

slutarius said:
You can do back-annotation simulation using SPEF of SDF plus the netlist which can be exported from ICC.
Then, input them to a simulator VCS, ModelSim ....
Click to expand...

Thanks for your response.

Is this SPEF file ready for use in Hspice? Or it needs modification?Can I just simulate it and see the results?

Thank you for your help in advance.
 

You are missing some fundamentals here. Your questions don't make sense. You can't spice a verilog file because that is not spice. You can't convert a verilog file to spice because verilog only has connectivity, it has no locations or even routing.

Have you ever used an environment like virtuoso? Do you know what a stream in, stream out is? Those are the questions you should be asking.
 

marjang said:
Thanks for your response.

Is this SPEF file ready for use in Hspice? Or it needs modification?Can I just simulate it and see the results?

Thank you for your help in advance.
Click to expand...

No. Spef is only used for timing calculation and back-annotation. The standard cell and macro libraries are required.

What is the purpose of your simulation ?
Function ? Timing ? or Transient aspect ?
 

slutarius said:
No. Spef is only used for timing calculation and back-annotation. The standard cell and macro libraries are required.

What is the purpose of your simulation ?
Function ? Timing ? or Transient aspect ?
Click to expand...

I have the libraries for standard cells and macros. What else do I need? I really do not know how should I do post layout simulation :-( If you could help me or provide some tutorial that can be a help, I would appreciate you.

I forgot to say about the purpose of simulation, yes it is for checking the functionality of the design.

Thank you in advance.
 

If you are trying to verily the timing functionality you need to write out a Verilog/VHDL netlist and the corresponding SDF files for all the corners (using the Spef as slutarius mentions). Hopefully you have a set of regression tests that you can run on the netlist that you used for verifying the functionality of the RTL originally.

If you only care about functionality (not timing) then run the simulation on the Verilog netlist with no SDF to see if logically it's still the same design or better yet use formal tools to verify that.
 

ads-ee said:
If you are trying to verily the timing functionality you need to write out a Verilog/VHDL netlist and the corresponding SDF files for all the corners (using the Spef as slutarius mentions). Hopefully you have a set of regression tests that you can run on the netlist that you used for verifying the functionality of the RTL originally.

If you only care about functionality (not timing) then run the simulation on the Verilog netlist with no SDF to see if logically it's still the same design or better yet use formal tools to verify that.
Click to expand...

Thanks for replying.

I am going to use Hspice for simulation. Is there any way to extract hspice netlist from IC compiler not the verilog netlist? Or do you know any toll for converting verilog to hspice netlist?

Thank you in advance.
 

marjang said:
Thanks for replying.

I am going to use Hspice for simulation. Is there any way to extract hspice netlist from IC compiler not the verilog netlist? Or do you know any toll for converting verilog to hspice netlist?

Thank you in advance.
Click to expand...
This answer you got back in post #2
ThisIsNotSam said:
err, no. you need to extract first, then use the extracted netlist with hspice.

since you have used ICC, I assume this is a decent sized digital design. be aware that hspice simulation might not be feasible.
Click to expand...

Unless this design is very small and/or you are using a supercomputer. I really think you should rethink what you are trying to accomplish. So what if the other engineer simulates something in HSPICE. How do you know that doing so is applicable in your situation. If they did HSPICE simulation on a few gates or some other cells then that makes sense, but on an entire ASIC...

Hope you live long enough to run a 100 us simulation on your HSPICE netlist of a 10M gate ASIC. ;-)
 

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