Layout:If my available pads on IC is less than the required by my various circuits?

Layout:If my available pads on IC is less then the required by my various circuits?

My question is - Suppose i am planning to send my 4-5 big circuits for tapeout on a single IC and area is sufficient to me but the pads provided by my foundry for this chip size are less in nos. What is the other way to get my circuit done and test all the individual circuit on chip.

my sol.- Can is make extra pads in the middle of chip where (not at the boundary of chip) my block/circuit present. In this case i don't have option of taking bond wire out from chip (for pads drawn in middle of chip) while packaging but i think without packaging, i will be able to test it. If testing all circuits is my primary goal and using some important circuit on chip is okay to me.

What do you say? I am new in this fabrication/testing things of chips. kindly provide some solution and will my solution work if i don't want to use few circuit after packaging but like to test on unpackaged chip.


ps- restriction = fixed no. of available on boundary of chip and i can't go for bigger area to avail more no. of pads.




"Take a step forward and things will start happening"
~Rahul

Re: Layout:If may available pads on IC is less then the required by my various circui

I have many times made either concentric pad rings (sometimes using
two-shelf packages, sometimes staggering the pads to minimize the
wire-over-opening hazards) or sea-of-pads (as is common on foundry
process characterization / control chip designs).

You need to think through the path to test (test chips) or production
(where stricter assembly / quality rules will be enforced) to see if
these approaches, or maybe a pad shrink, is the more appropriate
way to go.

You can also consider things like pad sharing or signal multiplexing /
demultiplexing depending on how independent sections might need
to be.

Re: Layout: If my available pads on IC are less than the required ones

Quite often in-circuit test pads with quadratic sizes of 20 or even 10µm edge length are used. Ask your foundry or fab about this opportunity.

Also, think of sufficient drive capability for external test input impedance.