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Using WHEN command during Portmap

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sreevenkjan

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Hi all,

I am trying to portmap a signal using WHEN command.

for example in the code below

Code: 
port map
(
x => '1',
a => (b when (x='0') else c),
y => x"0"
);

I get the below error during compilation

Error (10500): VHDL syntax error at test.vhd(1710) near text "WHEN"; expecting ")", or ","
Click to expand...

am I right in using the WHEN command?? How am I supposed to change the code reading that error??

regards,
Sreeni
 
Last edited:

Not very sure, but I think a => (b when (x='0') else c), is not allowed during portmap in VHDL.
Just declare another signal and do the logic assignment to it. Then use that signal for portmap.

Code: 
my_signal <= <<whatever you want to do>>; 

a => my_signal;

I would rather use the "with....select"

Code: 
with x select out <= b when '0', c when others;
 
Last edited:

Well I did try that but since the component for which I am port mapping is a transmitter block, it sends me an error telling that the portmapped signal should be an FPGA input signal. the input signal from the FPGA is to be portmapped with the transmitter clock from the transmitter block.
 

, it sends me an error telling that the portmapped signal should be an FPGA input signal.
Click to expand...

As far as I know an output port, input port or an internal signal can be port mapped. I don't understand what you say!
 
Last edited:

There are several problems here: First of all, you cannot do complex assignments in a port map. For '93 you cannot call functions in a port map, but in VHDL 2008 you can.
You cannot use when because "when" is not a function, and doesnt return anything, its a built in operator that works with the assignment operator (again, assignment is not a function). You will need a temporary signal.

Another confusing aspect, when cannot be used inside a process in '93 as it's meant for constant assignments, but in '08 you can (along with with/select).

Also, I not you're using x in the when assignment. This will have to be X defined in the architecture, NOT the X from the port map (as you have no visibility of these names).

Code VHDL - [expand]
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signal a : std_logic;
 
port map
(
x => '1',
a => a,
y => x"0"
);
 
a <= b when (x='0') else c;  -- this assumes x is declared locally
 

TrickyDicky said:
There are several problems here: First of all, you cannot do complex assignments in a port map. For '93 you cannot call functions in a port map, but in VHDL 2008 you can.
You cannot use when because "when" is not a function, and doesnt return anything, its a built in operator that works with the assignment operator (again, assignment is not a function). You will need a temporary signal.

Another confusing aspect, when cannot be used inside a process in '93 as it's meant for constant assignments, but in '08 you can (along with with/select).

Also, I not you're using x in the when assignment. This will have to be X defined in the architecture, NOT the X from the port map (as you have no visibility of these names).

Code VHDL - [expand]
1
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3
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signal a : std_logic;
 
port map
(
x => '1',
a => a,
y => x"0"
);
 
a <= b when (x='0') else c;  -- this assumes x is declared locally
Click to expand...

Hi Tricky,

you are right, I am not using x as input. It was just an example. How do you use when in 08 VHDL. I changed the project settings with vhdl input as 2008 version but still got the same error.
 

but since the component for which I am port mapping is a transmitter block, it sends me an error telling that the portmapped signal should be an FPGA input signal.
Click to expand...
In other words you are trying to feed a dedicated hardware input (e.g. a transmitter clock or data input) from FPGA fabric. Unless you find specific features allowing this connection, It doesn't work.

It's a problem of FPGA properties, not a HDL problem. Review the FPGA hardware manual about possible sources for the respective signal.
 

FvM said:
In other words you are trying to feed a dedicated hardware input (e.g. a transmitter clock or data input) from FPGA fabric. Unless you find specific features allowing this connection, It doesn't work.

It's a problem of FPGA properties, not a HDL problem. Review the FPGA hardware manual about possible sources for the respective signal.
Click to expand...

I am trying to feed a clk signal as input to the Tx input clock, so I have a register which controls the input clock to the tx input clk. The control is based on if my tx pll is locked or unlocked. however surprisingly the tx input receives clock from an internally PLL generated clock.
 

Can you provide the actual error?

You should also look into using the clocking primitives. More complex clocking schemes can introduce setup/hold issues. For example, switching clocks can result in a glitch if one clock is high and the other is low and about to transition.
 

however surprisingly the tx input receives clock from an internally PLL generated clock.
Click to expand...
What's surprising here?

Clock networks have a number of constraints related to the jitter and skew performance. They are clearly specified in FPGA hardware manuals. If you are asking about Altera FPGA, a clock control block may be used to switch between clock sources.
 

vGoodtimes said:
Can you provide the actual error?

You should also look into using the clocking primitives. More complex clocking schemes can introduce setup/hold issues. For example, switching clocks can result in a glitch if one clock is high and the other is low and about to transition.
Click to expand...

the actual error like I pointed above is

Error (10500): VHDL syntax error at test.vhd(1710) near text "WHEN"; expecting ")", or ","
Click to expand...
 

sreevenkjan said:
the actual error like I pointed above is
Click to expand...

This error is just a syntax error.
What FvM and vGoodTimes are talking about are more fundamental problems in your design, as you appear to be trying to mux a clock, which is not something that should be done without proper design consideration and is not something that is fixed in VHDL.
 

TrickyDicky said:
This error is just a syntax error.
What FvM and vGoodTimes are talking about are more fundamental problems in your design, as you appear to be trying to mux a clock, which is not something that should be done without proper design consideration and is not something that is fixed in VHDL.
Click to expand...

yes I get that problem. well the current problem is I would like to give a signal to the tx clock based on the PLL lock status. The problem is I cannot connect any signal to the tx clock. I have 2 clocks which I want to connect to tx. During the initialization I want to connect a intern PLL generated clock but later I would like to connect a external ref clock.

The question is how can I connect tx clock to any of these 2 clocks based on my pll lock status without using a third signal.
 

sreevenkjan said:
I have 2 clocks which I want to connect to tx. During the initialization I want to connect a intern PLL generated clock but later I would like to connect a external ref clock.

The question is how can I connect tx clock to any of these 2 clocks based on my pll lock status without using a third signal.
Click to expand...

Seems to me FvM already mentioned using a clock control block back in post #10 and if you are using a Xilinx device the BUFGCTRL (7-series, a BUFGMUX in earlier devices) will allow switching between two clocks.

You should look up the primitives documentation on whichever device manufacturer you are using and then return and ask any questions.

..., it sends me an error telling that the portmapped signal should be an FPGA input signal. the input signal from the FPGA is to be portmapped with the transmitter clock from the transmitter block.
Click to expand...
But without any useful information besides this, perhaps the problem lies in the code of the transmitter block, which might already have I/O cells instantiated in the code. Have you looked in the source code of this transmitter?
 

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