the problem of Axi4 Lite BReady does not asserted in the xilinx Vivado.

Hi.

I'm trying to implement the fifo in the vivado.
the fifo which is based on axi4 lite prtocal.

I just made one maser and interconnect and fifo_generator.

The problem is that I issue the awaddr and wdata and checked awready and wready but Bready does not asserted in the progress.

Does anyone give to me any hint what should I check to do ?

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Sorry BVALID not bready

You really ought to read Xilinx document PG057, which describes the AXI4, AXI4-Lite and AXI4-Stream interfaces to the Xilinx FIFOS.

Table 1-8 explains that the BVALID signals are used as EMPTY flags. So if it is not asserting, then you are attempting to read from an empty FIFO.

r.b.

rberek said:

You really ought to read Xilinx document PG057, which describes the AXI4, AXI4-Lite and AXI4-Stream interfaces to the Xilinx FIFOS.

Table 1-8 explains that the BVALID signals are used as EMPTY flags. So if it is not asserting, then you are attempting to read from an empty FIFO.

r.b.

Click to expand...

Thanks, I'm confused after read the document, then the fifo does not follow axi interface?

In AXI4 , VALID and READY signals are used as flow control on each channel, with the provider of data on the channel asserting VALID to let the consumer of data know it has data to send. On a Xilinx FIFO, the EMPTY flag serves the same purpose. It lets the consumer of the data know whether or not there is data to consume.

The document says that the AXI4 interface is a wrapper around the native-interface FIFO. Thus, using the VALID signal as an EMPTY signal makes perfect sense, and follows the spirit, if not the letter, of the AXI4 spec.

Does it follow the AXI4 spec exactly? I don't know. It has been a few years since I used AXI4. But as a designer, as long as I understand what Xilinx is doing, it doesn't really matter. I will design the interfacing circuitry to work with Xilinx's interpretation of the AXI4 spec. If I am using legacy AXI4 IP, i will design glue logic to make it work.

Why do you think it does not follow the spec?

r.b.

u24c02,

read this post:
http://forums.xilinx.com/t5/Embedde...I-handshaking-process-VALID-READY/td-p/454000