shaiko
Advanced Member level 5
Hello,
This is my code:
I simulated the above in Modelsim.
I expected bit #0 of x to always be 0. But it's 'U'.
Is it a bug ?
This is my code:
Code:
signal x : std_logic_vector ( 7 downto 0 ) ;
x ( 0 ) <= '1' ;
strange : process ( CLOCK , RESET ) is
begin
if RESET = '1' then
x ( 7 downto 1 ) <= ( others => '0' ) ;
elsif rising_edge ( CLOCK ) then
for index in 0 to 6 loop
x ( index + 1 ) <= x ( index ) ;
end loop ;
end if ;
end process strange ;
I simulated the above in Modelsim.
I expected bit #0 of x to always be 0. But it's 'U'.
Is it a bug ?