[SOLVED] Verilog parameters used in port dimensions

wtr · Jul 13, 2016

Hello all,

I'm curious about how I can do the following in verilog

Code VHDL - [expand]
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entity PARITY is
  generic (N : integer);
  port    (A : in std_ulogic_vector
                  (N-1 downto 0);
         ODD : out std_ulogic);
end PARITY;

I'm aware of parameters. I want to code in verilog 2001 or 2005.
Can I do the following

Code Verilog - [expand]
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module parity (
  input [N-1:0] A,
  output          ODD
);
parameter integer N=8

The reason I'm having doubts is because the N is declared after the use.
The internet just seems to have all the old stuff anyone got a good tutorial for 2001 or 2005 syntax.

Then when instantiated in the module I expect something like the following

Code Verilog - [expand]
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parity #(.N(16)) UUT(
  .A(my_in_sig),
  .ODD(my_out_sig)
);

Being a vhdl guy it hurts to not instantiate as
module_name module_instance #param #ports

Thanks
Wes

ads-ee · Jul 13, 2016

Code Verilog - [expand]
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module parity #(
  parameter integer N=8
) (
  input [N-1:0] A,
  output        ODD
);

-- edit

wesleytaylor said:
The internet just seems to have all the old stuff anyone got a good tutorial for 2001 or 2005 syntax.

Check this paper https://www.sutherland-hdl.com/papers/2000-HDLCon-paper_Verilog-2000.pdf

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[SOLVED] Verilog parameters used in port dimensions

wtr

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wtr

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