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Capacitance load lead ringing or osillation

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Johnny_YU

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Hi,

I find a lot of articles say: high capacitance loads can lead ringing or even severe osillation in power line.

I don't understand.

I think when drive a capacitance load , the load will draw more current from power supply. Because of the resistor of power supply, the supply voltage will droop. but why power line will ring or osillate?
 

Power lines have considerable inductance. If the load is considerably capacitive, there will be ringing- the resistance of the load will decide the decay time constant. You cannot completely eliminate but you can adjust some parameters to make it critically damped.
 
Every time you switch that capacitance you spike either
the power or the ground rail and this has to damp out,
if indeed it can; ground kicks especially get into all kinds
of other things (like your reference voltage, your current
sense, etc.) and can initiate large signal instability even
in "small signal stable" loops.

The higher you make power network C and Q (in the
interests of efficiency and noise) the longer it's going
to take the bypassing to "ring down". And I've seen
this (unsettled VDD) cause polymodal duty cycle
instability as it sneaks into the high side current
comparator of an integrated buck converter. All
stemming from the supply ringing that followed a
preceding switch event.
 
c_mitra said:
Power lines have considerable inductance. If the load is considerably capacitive, there will be ringing- the resistance of the load will decide the decay time constant. You cannot completely eliminate but you can adjust some parameters to make it critically damped.
Click to expand...

Hi,c_mitra

Thank you for your reply!

you mean ,i shuold think that like a RCL circuit? if i need to model it, i shuold choose a parallel RCL or a series RCL circuit?

have you got any articles about explaining this situation?
 

Johnny_YU said:
,i shuold think that like a RCL circuit? if i need to model it, i shuold choose a parallel RCL or a series RCL circuit?
have you got any articles about explaining this situation?
Click to expand...

Right, an ideal power supply has ZERO impedance (internally) and DOES not induce ringing in the power line side. It can induce ringing on the load side but that is independent of the power supply impedance.

Yes, you should model this as a RCL circuit; in absence of additional information, you will need to try both series and parallel cases and match the results with observations. This is important with derived power supplies (SMPS, for example) and less important with direct power lines (they are mostly matched).

Sorry, I do not have a reference right on hand.
 
Long power lines themselves are inductive, and the transformers used for voltage changing even more so.
Lumped capacitors are also often added for power factor correction.

Try an internet search about "surge impedance".
Its all a lot more complicated than it at first appears.
 
dick_freebird said:
Every time you switch that capacitance you spike either
the power or the ground rail and this has to damp out,
if indeed it can; ground kicks especially get into all kinds
of other things (like your reference voltage, your current
sense, etc.) and can initiate large signal instability even
in "small signal stable" loops.

The higher you make power network C and Q (in the
interests of efficiency and noise) the longer it's going
to take the bypassing to "ring down". And I've seen
this (unsettled VDD) cause polymodal duty cycle
instability as it sneaks into the high side current
comparator of an integrated buck converter. All
stemming from the supply ringing that followed a
preceding switch event.
Click to expand...

Hi, dick_freebird

Thank you for reply!

I don't totally understand your reply about ground kick. i will seach for that , then i will back,thank you!

- - - Updated - - -

dick_freebird said:
Every time you switch that capacitance you spike either
the power or the ground rail and this has to damp out,
if indeed it can; ground kicks especially get into all kinds
of other things (like your reference voltage, your current
sense, etc.) and can initiate large signal instability even
in "small signal stable" loops.

The higher you make power network C and Q (in the
interests of efficiency and noise) the longer it's going
to take the bypassing to "ring down". And I've seen
this (unsettled VDD) cause polymodal duty cycle
instability as it sneaks into the high side current
comparator of an integrated buck converter. All
stemming from the supply ringing that followed a
preceding switch event.
Click to expand...

Hi, dick_freebird

Thank you for reply!

I don't totally understand your reply about ground kick. i will seach for that , then i will back,thank you!
 

Johnny_YU said:
you mean ,i shuold think that like a RCL circuit? if i need to model it, i shuold choose a parallel RCL or a series RCL circuit?
Click to expand...

From the ringing frequency (you do not need great accuracy) you can get the LC product and the decay rate you can get the RC value. You need to *guess* which is contributed from the power line (L or C; not the R I presume) and tweak the other (the one you have some control, hopefully) to make it critically damped.
 
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