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[SOLVED] well proximity effect TSMC65

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vaah

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Hello everyone,

I have a quesion about well proximity effect(WPE) in tsmc65.

I have an issue with WPE. When i create Calibre view and compare the post layout result with schematic I am observing a huge difference. I found that it occurs because of that in the schematic "WPE" is off and it will be on for Calibre. The most interesting part is that it happens just for NMOS IO devices! I would appreciate it if you could help me to figure it out! what do I need to do?
DO I need to active "WPE" is schematic or I should uncheck "WPE" in Calibre view?

Many thanks.
 

... or I should uncheck "WPE" in Calibre view?

No, because Calibre tries to give you helpful info, however you - as the designer/user - needs to judge where this info is important. WPE is important for structures to be well matched, like, e.g., differential input transistors, current mirrors, any structure pairs/multiples where matching is important. This is not so much the case for IO structures, I'd think. If anyway, try to get around by keeping more spacing between the affected structure and its next well border.
 

No, because Calibre tries to give you helpful info, however you - as the designer/user - needs to judge where this info is important. WPE is important for structures to be well matched, like, e.g., differential input transistors, current mirrors, any structure pairs/multiples where matching is important. This is not so much the case for IO structures, I'd think. If anyway, try to get around by keeping more spacing between the affected structure and its next well border.


Thank you so much

The thing is that Im just simulating a simple diode-connected transistor (just one transistor)
there is no other trasistor!

https://obrazki.elektroda.pl/6072136300_1468057392.jpg
 

No, because Calibre tries to give you helpful info, however you - as the designer/user - needs to judge where this info is important. WPE is important for structures to be well matched, like, e.g., differential input transistors, current mirrors, any structure pairs/multiples where matching is important. This is not so much the case for IO structures, I'd think. If anyway, try to get around by keeping more spacing between the affected structure and its next well border.

Ive tried to put a dummy poly alone in layout but it gives an error. Should i put dummy transistor in schematic as well?
 

Im just simulating a simple diode-connected transistor (just one transistor) there is no other trasistor!
https://obrazki.elektroda.pl/6072136300_1468057392.jpg

So you don't have to mind about the WPE effect. If the postLayout results suggest a different current-voltage characteristic, correct it by changing the W/L ratio.

- - - Updated - - -

Ive tried to put a dummy poly alone in layout but it gives an error. Should i put dummy transistor in schematic as well?

You always have to mention the layout dummies in the schematic view, too, otherwise the LVS will give an error.

But in your case you don't need a dummy. Just give it a wider nwell, so your transistor is farer from the nwell border - this should minimize the WPE error.

Or adjust the W/L ratio up to your need, as suggested above.
 

So you don't have to mind about the WPE effect. If the postLayout results suggest a different current-voltage characteristic, correct it by changing the W/L ratio.

- - - Updated - - -



You always have to mention the layout dummies in the schematic view, too, otherwise the LVS will give an error.

But in your case you don't need a dummy. Just give it a wider nwell, so your transistor is farer from the nwell border - this should minimize the WPE error.

Or adjust the W/L ratio up to your need, as suggested above.

Thank you for your response. I really appreciate it
You recommend to not use same NWELL for PMOS transistors, right?

- - - Updated - - -

So you don't have to mind about the WPE effect. If the postLayout results suggest a different current-voltage characteristic, correct it by changing the W/L ratio.

- - - Updated - - -



You always have to mention the layout dummies in the schematic view, too, otherwise the LVS will give an error.

But in your case you don't need a dummy. Just give it a wider nwell, so your transistor is farer from the nwell border - this should minimize the WPE error.

Or adjust the W/L ratio up to your need, as suggested above.

I am a little bit confused! We say that we must put transistor as close as possible for better matching and from the other side we put them in different well coz of WPE!
 

Thank you for your response. I really appreciate it
You recommend to not use same NWELL for PMOS transistors, right?
Not at all.

... Im just simulating a simple diode-connected transistor (just one transistor)
there is no other trasistor!
Until now, you just talked about one single PMOS transistor, didn't you?

- - - Updated - - -
I am a little bit confused! We say that we must put transistor as close as possible for better matching and from the other side we put them in different well coz of WPE!

Total misunderstanding! Transistors to be matched as close as possible of course, with dummies at both sides if necessary. But the nwell wide enough, with many n+ nwell taps (even better: n+ nwell tab ring) between the transistor(s) and the nwell border, with contacts to metal1 and connection to VDD. So you shouldn't get WPE errors.
HTH!
 

Total misunderstanding! Transistors to be matched as close as possible of course, with dummies at both sides if necessary. But the nwell wide enough, with many n+ nwell taps (even better: n+ nwell tab ring) between the transistor(s) and the nwell border, with contacts to metal1 and connection to VDD. So you shouldn't get WPE errors.
HTH!

So you mean that all transistors must have their own well and gaurdring! like the attached p

https://obrazki.elektroda.pl/2904504400_1468356779.png
 

So you mean that all transistors must have their own well and gaurdring!

No, they can have a common well, and a common n+ tap ring is fine. A p+ guard ring should be outside of and surrounding the nwell, with contacts to metal1 and connection to GND.
 

No, they can have a common well, and a common n+ tap ring is fine. A p+ guard ring should be outside of and surrounding the nwell, with contacts to metal1 and connection to GND.

Thank you so much for your time and help

I am not familiar with the NTAP word! NTAP is used for bulk connection, right? (I am talking about PMOS transistors)


For a PMOS transistors, we use nwell ring for bulk connection connected to VDD and P+ ring outside of the whole nwell connected to GND!
 

I am not familiar with the NTAP word! NTAP is used for bulk connection, right? (I am talking about PMOS transistors)

TAP is a connection location for something - like a water tap for water. An NTAP (or n-tap or n+ tap) is the heavily (+)doped connection location for a weakly (-)doped n- region, e.g. an nwell. So it's an NTAP for the nwell: It is quasi tapping the nwell.

I'd suggest you study the short (just 33 pages) and well illustrated by Lee Eng Han et al. There's a short explanation for TAP at page 7 .

For a PMOS transistors, we use nwell ring for bulk connection connected to VDD and P+ ring outside of the whole nwell connected to GND!

For PMOS transistors, we use n+well tap ring for bulk connection of the PMOS in nwell connected to VDD, and a P+ ring on substrate outside of the whole nwell connected to GND.
Right!
 

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