vaah
Member level 3
Hello everyone,
I have a quesion about well proximity effect(WPE) in tsmc65.
I have an issue with WPE. When i create Calibre view and compare the post layout result with schematic I am observing a huge difference. I found that it occurs because of that in the schematic "WPE" is off and it will be on for Calibre. The most interesting part is that it happens just for NMOS IO devices! I would appreciate it if you could help me to figure it out! what do I need to do?
DO I need to active "WPE" is schematic or I should uncheck "WPE" in Calibre view?
Many thanks.
I have a quesion about well proximity effect(WPE) in tsmc65.
I have an issue with WPE. When i create Calibre view and compare the post layout result with schematic I am observing a huge difference. I found that it occurs because of that in the schematic "WPE" is off and it will be on for Calibre. The most interesting part is that it happens just for NMOS IO devices! I would appreciate it if you could help me to figure it out! what do I need to do?
DO I need to active "WPE" is schematic or I should uncheck "WPE" in Calibre view?
Many thanks.