audio processor sta321mp inquiries

Greetings everyone, currently i am working on my thesis and i am planning to use this IC (STA321MP) for my proyect as it fits the requierments that i am proposing for it, but there are some specific points and doubts that i can not solve along side the data sheet so that´s why i am writing this request. The questions goes as follows:

1) What is main function or porpouse of the Dual Flip Flop than can be seen in the image below? Is this one located inside the STA321MP or is and external component?



2) How does the PLL (phase locked_loop) ratio is program orr set? is not very clear on the data sheet.

3) What is the purpouse of the PLL_BYPASS pin ? Its functionality overall.

4) The subject around the PDM_CLK and how to obtain the CKOUT frequency is not very clear for me, could you please help me to understand it in a simpler way.

5) The sampling frequency that is said on the datasheet of the STA321P supports a 2.8224Mhz frequency with a internal fixed clock of 90.3168 hz, Is it a fixed default value? is it variable or i can be set apart?

Time is of scense for me, i would apreciate any help you can provide me. Thanks before hand.

Here is a link to the datasheet of the sta321mp:

https://www.st.com/content/ccc/resource/technical/document/datasheet/group3/f8/d2/89/64/7e/28/4d/11/DM00046002/files/DM00046002.pdf/jcr:content/translations/en.DM00046002.pdf

Good Day.

carsacc said:

1) What is main function or porpouse of the Dual Flip Flop than can be seen in the image below? Is this one located inside the STA321MP or is and external component?

Click to expand...

The flip-flop says 'CK divider'. This implies it divides the clock pulses by 2, in order to make 50 percent duty cycle. It is a common role for a flip-flop. The 'D' type is easy to use in this role.

The word 'dual' is puzzling, because a single flip-flop is indicated in that position. Perhaps it said 'D Flip/flop' originally, and the artist thought it meant 'dual'?

2) How does the PLL (phase locked_loop) ratio is program orr set? is not very clear on the data sheet.

Click to expand...

This is all in section 5 of the data sheet. The I2C protocol is used to set and read the registers.

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3) What is the purpose of the PLL_BYPASS pin ? Its functionality overall.

Click to expand...

I'd suspect that the PLL_BYPASS or PLLB pin will cause that the PLL will not be used for the internal clock signal. Rather, a clock signal could be directly driven into the digital logic. I'd think this would be for chip testing and that you don't need to use it. Hence, the datasheet doesn't get into it.