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How do we set time in vhdl simulation for an fpga kit having clock of 100 MHz?

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Anwesa Roy

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We are writing a code in vhdl. How do we set time in vhdl simulation for an fpga kit having clock of 100 MHz? Should we set it to 10ns(10 nano seconds) for effective viewing of results? Where should we do it?...In the encircled portion of the first figure or the encircled portion of the second figure?
first figure:
Picture1.png
second figure:
picture2.png
And kindly tell us the significance of the encircled portion in fist and second figures respectively.
 
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If f=100Mhz, T=10ns
That mean the clk signal will toggle every 5ns.
So ns resolution should be sufficient.

There is no option to set the default timescale of the Waveform window before opening it (might be version dependent). Once it is opened you can adjust it by doing a right click anywhere in the waveform window and select the desired timescale.

There are also TCL commands.

Hope this is what you want, how to do it from the GUI.

-----------------------------

The 2nd pic, which you uplaoded just a few sec. ago!
Why are you forcing the signal (clock)?

Your clock should be driven from the testbench, which will apprear in the sim waveform.
 

The first picture shows how long pushing the |> (T) button (next to the 10 us box) will run the simulation for. It has nothing to do with the scaling of the waveform view itself.

The second picture shows the clock period (which dpaul alluded to) you are defining, in this case 10 ns (i.e a 100 MHz clock), this also has nothing to do with either the run time in the first picture or the waveform viewer scale.
 
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