msdarvishi
Full Member level 4
Hello,
I am working with ISE 14.7 targeting a Virtex-5 FPGA. I manually placed and routed some components of my design. I know that those new constraints (PLACE&ROUTE) are written automatically in PCF file. But I am wondering to know how can I export the manual routing and placement constraints from FPGA Editor to the main UCF of my design??
In the following link it was written : " If you want to maintain both routing and placement, export the directed routing constraints to the UCF file" .... but how to do it??
https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_imp_strategies_using_fpga_editor.htm
Kind replies are in advance appreciated.
Thanks and Regards,
I am working with ISE 14.7 targeting a Virtex-5 FPGA. I manually placed and routed some components of my design. I know that those new constraints (PLACE&ROUTE) are written automatically in PCF file. But I am wondering to know how can I export the manual routing and placement constraints from FPGA Editor to the main UCF of my design??
In the following link it was written : " If you want to maintain both routing and placement, export the directed routing constraints to the UCF file" .... but how to do it??
https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_imp_strategies_using_fpga_editor.htm
Kind replies are in advance appreciated.
Thanks and Regards,
