Why AXI LITE has 4K address boundary limited?

Hi.

Now I'm trying to use AXI LITE. But I found something that the address boundary has 4K.

I think this is very wasting address space.

Can you let me know why that has 4K boundary?

I think this is very wasting address space.

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Try reporting it directly to ARM. Post this in ARM AMBA forums.

Normally I avoid such Qs, but I want to be cheerful on a Monday morning, considering the long week ahead!

dpaul said:

Try reporting it directly to ARM. Post this in ARM AMBA forums.

Normally I avoid such Qs, but I want to be cheerful on a Monday morning, considering the long week ahead!

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Hmm... The ARM question have to go ARM forum, Cadence question have to go Cadence...Synopsys question have to go Shnopsys?

Because that 4k boundary is what is defined in the AMBA specs.

As I have replied in the FPGA forums today mornings, you again didn't care to do a search for your question before posting here.
Your 4K limitation is explained in many places. One of this is ....
https://community.arm.com/thread/3137

It's exactly as the ARM spec states - to keep the size of the adders that increment the address down, so that they are small and fast (as each slave must have its own).

Address space isn't wasted - a slave's address space can be much larger than 4k, you just can't have a single burst that crosses the boundary.

jbeniston said:

It's exactly as the ARM spec states - to keep the size of the adders that increment the address down, so that they are small and fast (as each slave must have its own).

Address space isn't wasted - a slave's address space can be much larger than 4k, you just can't have a single burst that crosses the boundary.

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Thanks, as you said, "a slave's address space can be much larger than 4k,". I can't understand it how can a slave address space can be much larger than 4k?

It can be anything - you just can have a single burst transaction that crosses a 4k boundary.

jbeniston said:

It can be anything - you just can have a single burst transaction that crosses a 4k boundary.

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I think you meant that you can not have a single burst transaction that crosses a 4K boundary.

As for AXI Lite (I thought is was AXI4 Lite and I'm currently looking at the spec itself, the latest, including the AMBA AXI one from 2003 and there is no mention of an AXI-Lite)...AXI4 Lite only supports single cycle transactions. See section B1.1 Definition of AXI4-Lite:

This section defines the functionality and signal requirements of AXI4-Lite components.
The key functionality of AXI4-Lite operation is:
• all transactions are of burst length 1
• all data accesses use the full width of the data bus
— AXI4-Lite supports a data bus width of 32-bit or 64-bit.
• all accesses are Non-modifiable, Non-bufferable
• Exclusive accesses are not supported.

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The 4K boundary only applies to non-Lite.

A3.4.1 Address structure
The AXI protocol is burst-based. The master begins each burst by driving control information and the address of
the first byte in the transaction to the slave. As the burst progresses, the slave must calculate the addresses of
subsequent transfers in the burst.
A burst must not cross a 4KB address boundary.
Note
This prevents a burst from crossing a boundary between two slaves. It also limits the number of address increments
that a slave must support.

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So besides the OP asking an invalid question (burst transactions on the non-existent AXI-Lite), the OP hasn't read (or perhaps understood) the AMBA AXI and ACE Protocol Specification document (where the AXI4-Lite is specified).

u24c02 please research topics before posting on edaboard. Due to the lack of research effort on your part, many of our more helpful members may have begun to ignore your threads.