logari84
Newbie level 6
SystemVerilog, "struct packed", module mapping issue in Encounter RTL compiler
Hi all,
I am trying to synthesize a design with Encounter RTL but I am having problems with a struct. I am using many structs so I am posting only one as an example.
Let's say I am using this which is defined in a separate file containing all typedefs:
Top module:
PR_ADDRESS_WIDTH = 16 and BITS_PER_ADC = 4. So this means that data_in is a signal of total 32 bits ([15:0][3:0][3:0][3:0][3:0])
encoder module (the one instantiated within Top)
In ModelSim I get no errors, no warnings and the ports are mapped correctly. Though when I try to run the synthesis with Encounter RTL, I get a warning about signal width mismatch. To be more specific the tool tries to map the whole 32-bit data_in of the Top module to the 4-bit data_in.adc3 in the encoder data_in port. So either I am doing something wrong, or mapping a struct in module ports is not supported.
Any hints??
Thank you in advance.
- - - Updated - - -
Hmm... I probably found what I was doing wrong. It seems that the .* implicit port connection was the solution. I changed encoder enc_unit(clk, en, data_in, enc2pckg); with encoder enc_unit(.* , .data_out(enc2pkg)); and I only got some warnings that I don't think is something important.
Hi all,
I am trying to synthesize a design with Encounter RTL but I am having problems with a struct. I am using many structs so I am posting only one as an example.
Let's say I am using this which is defined in a separate file containing all typedefs:
Code:
typedef struct packed{
logic[`PR_ADDRESS_WIDTH-1:0] address;
logic[`BITS_PER_ADC-1:0] adc0;
logic[`BITS_PER_ADC-1:0] adc1;
logic[`BITS_PER_ADC-1:0] adc2;
logic[`BITS_PER_ADC-1:0] adc3;
} T_PR_DATA;Top module:
Code:
`include "constants.sv"
`include "types.sv"
module Top_compressor(clk, en, data_in, data_out);
input clk;
input en;
input T_PR_DATA data_in;
output reg [31:0] data_out;
T_ENCODED_ADDR_ADC enc2pckg;
encoder enc_unit(clk, en, data_in, enc2pckg);
endmodulePR_ADDRESS_WIDTH = 16 and BITS_PER_ADC = 4. So this means that data_in is a signal of total 32 bits ([15:0][3:0][3:0][3:0][3:0])
encoder module (the one instantiated within Top)
Code:
`include "types.sv"
`include "ROM_adc_code.sv"
module encoder(
input logic clk,
input logic en,
input T_PR_DATA data_in,
output T_ENCODED_ADDR_ADC data_out
);
assign data_out.address = data_in.address;
ROM_adc_code adc0_code_LUT(
.clk(clk),
.address(data_in.adc0),
.code(data_out.adc0_code),
.CS(1'b1)
);
ROM_adc_code adc1_code_LUT(
.clk(clk),
.address(data_in.adc1),
.code(data_out.adc1_code),
.CS(1'b1)
);
ROM_adc_code adc2_code_LUT(
.clk(clk),
.address(data_in.adc2),
.code(data_out.adc2_code),
.CS(1'b1)
);
ROM_adc_code adc3_code_LUT(
.clk(clk),
.address(data_in.adc3),
.code(data_out.adc3_code),
.CS(1'b1)
);
endmoduleIn ModelSim I get no errors, no warnings and the ports are mapped correctly. Though when I try to run the synthesis with Encounter RTL, I get a warning about signal width mismatch. To be more specific the tool tries to map the whole 32-bit data_in of the Top module to the 4-bit data_in.adc3 in the encoder data_in port. So either I am doing something wrong, or mapping a struct in module ports is not supported.
Any hints??
Thank you in advance.
- - - Updated - - -
Hmm... I probably found what I was doing wrong. It seems that the .* implicit port connection was the solution. I changed encoder enc_unit(clk, en, data_in, enc2pckg); with encoder enc_unit(.* , .data_out(enc2pkg)); and I only got some warnings that I don't think is something important.
