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zero creation in LDO regulator

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phanikiran

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How ESR and CLoad will create a zero? What is the operation ?
 

Its very simple. The impedance of ideal capacitor goes to 0 when frequency is infinite (in lin-log scale it is a straight line with negative slope). When You connect resistor in series with cap, at frequencies for which capacitor impedance is lower than resistance You start to see a constant value of impedance equal to resistance.

So for LDO point of view beyond this frequency gain stop decreased because load impedance becomes constant.
 
Does it mean Zero? How this (ESR+ Cload) can avoid or cancel a pole to make the LDO system stable?
 

Zero can be realized in many ways. Any RC R/L or 1/LC time constant could be either pole or zero depending on it location in transfer function (nominator or denominator). Any active element (eg transconductor) could realize a pole or zero.

In this example, zero is realized by blocking a gain roll-off made by output capacitor.
So if You have somewhere in a transfer function of your LDO a pole located at some frequency f1, if You match RC constant of ESR and load cap to be equal 1/2pi f1, You are able to cancel pole. From signal point of view it means that You are blocking path to ground and/or provide a new path to output for a signal with given frequencies.
 

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