salim.alam2
Junior Member level 3
I was trying to write a test bench and i got some problems
1. dose the testbench code should be in different file than the main code or both together in the same file?
2. I was trying to write a testbench to verify the behavior of a calculator including the error detection feature. I must verify that it detects errors, that error bit is cleared when a clear operation is performed and that other operations are blocked when the error bit is set, but it is not working
Could you please help
This is the testbench code that I wrote:
Thanks for your help
1. dose the testbench code should be in different file than the main code or both together in the same file?
2. I was trying to write a testbench to verify the behavior of a calculator including the error detection feature. I must verify that it detects errors, that error bit is cleared when a clear operation is performed and that other operations are blocked when the error bit is set, but it is not working
Could you please help
This is the testbench code that I wrote:
Code:
Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
Entity calculator_test is
end calculator_test;
Architecture test of calculator_test is
component calculator_1 is
Port ( clk : in std_logic; -- clock
Clear, load, add, complement : in std_logic; -- operation signals
Din : in std_logic_vector (15 downto 0); -- input data
Result : out std_logic_vector (15 downto 0)); -- output data
End component;
signal clk_test : std_logic := '0';
signal Clear_test, load_test, add_test, complement_test : std_logic;
signal Din_test, Result_test : std_logic_vector (15 downto 0);
begin
UUT : calculator_1
Port map ( clk => clk_test,
Clear => Clear_test,
load => load_test,
add => add_test,
complement => complement_test,
Din => Din_test,
Result => Result_test);
Testbench_process : process
begin
wait for 0 ns; Clear_test <='1';
assert (Result_test = "0000000000000000") report "Fail Clear" severity error;
wait for 10 ns; load_test <='1';
assert (Result_test = Din_test) report "Fail Laod" severity error;
wait for 10 ns; add_test <='1';
assert (Result_test = "1XXXXXXXXXXXXXXXX") report "Fail Add" severity failure;
wait for 10 ns; complement_test <='1';
assert (Result_test = not Din_test) report "Fail Complement" severity error;
wait for 10 ns;
end process;
end test;
Thanks for your help