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speed up simulation in Questasim

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bilal_oct

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I am running simulation at 100 ps resolution for 5000 m sec but it take more than 30 hours to complete the simulation.

Is there any way to speed up the Questasim simulation ?
 

If you haven't already done so, use compiler optimizations and only expose the modules/components you want to look at in the simulation with the +acc switch.
 

This sounds as though you want to examine 5 seconds operation of a circuit running at 1 GHz. It's an example of mixing micro and macro events. It becomes mismatched and unwieldy in simulation. (It is not a problem with real electronics, of course.)

Consider trying a longer timestep.
Also try a slower switching rate in your simulated circuit. You don't have to do the same in your real circuit. The aim is to examine approximate behavior, without having to wait 30 hours.

Set an initial charge on capacitors, so they don't start from zero.
 

Many things, but without knowing how you're currently running we can only guess.

- don't use -novopt
- stimulate for less time with several narrower scope test benches
-use the profiler to see where the bottleneck is
- use more behavioural models
 

Set an initial charge on capacitors, so they don't start from zero.

???, uh Questasim doesn't simulate capacitors, it's a VHDL/Verilog/SystemVerilog simulator. There are supposed to be ways to initialize a simulation with a "snapshot" of the simulation, but I've never figured out how to make that work in Modelsim let alone in Questa.

I also ran across an article ~5-10 years ago that made a point of not using mixed reference and precision, the person who wrote the article did a bunch of tests with long simulations with various combinations of reference and precision and discovered that running with identical reference and precision values was faster overall than mixed values. So a timescale of 1ps/1ps would be nearly identical in simulation performance as 1ns/1ns, but 1ns/100ps would have a large performance penalty. I've repeatedly tried to find this blog but have had no luck over the years. FYI this testing was done as I recall using VCS, so it may not apply to Questa at all.

I have noticed slight differences between using identical values and different ones, though admittedly I have not run the extensive tests that were on on that blog.
 

I am using this command to simulate.
vsim -t 100ps -voptargs=+acc source_lib.design_tb

I tried 500 ps but this gives error of invalid design which I guess maybe due to ram block which I have added in my design. Anyhow I will try to use optimize functions in the vsim command.

@ ads-ee:
Could you please explain little more about timescale of 1ps/1ps and 1ns/100ps ?
 

it's the Verilog `timescale directive. If you are using VHDL then it doesn't apply.
 

Is there any reason you need to use a ram model? If you are using a ram model and a model of the controller then you're in for some painfully slow sim times. If you are just trying to debug the behaviour of some of your RTL, why not just write a ram + controller model?
 

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