about choosing L for MOSfet

hello I am working on LNA design using TSMC 90nm CMOS process. the minimum L can be taken as 0.1 um but what is the maximum value of L that can be taken for CMOS. for eg, can i use the same model for L of 0.175 um or 0.3 um ???

In some cases you will find that the model makes up its
own mind about details based on L; even case-wise model
branches above and below some breakpoint. The foundry
modeling folks made that decision for you.

Or you may see NMOS devices "duplicated" with analog,
digital and RF transistors, each pointing to its own model
and with expected constraints on L, W, gate contacts
and so on, with differing tradeoffs in model accuracy /
complexity / solution speed (e.g. "digital" can be
expected to be minimum or near-minimum L, analog
longer L, RF minimum L with better gate contact rules
and maybe a narrower W limit, etc.).

In a LNA you almost never will want a longer than minimum
L (otherwise you are using too expensive a flow for the
frequency of interest).

PDK docs or the device properties form ought to constrain
the L values you can select by their callback functions.

But rf circuit design demands larger devices it's only for some transistors that you need minimum L for eg like feedback transistors but rest of the transistors like current sources etc requires devices with larger L

malhar said:

... can i use the same [L=0.1µm] model for L of 0.175 um or 0.3 um ?

Click to expand...

I'd think these lengths aren't so much longer that you couldn't use the min. length model. You can expect distinctly better (lower) g_ds (i.e. higher r_ds or V_A) values for longer L, see e.g. the foll. figure for an L_min=0.18µm process, which shows the CLM (channel length modulation) dependency on L :



Similar impacts on the δI_d/δV_ds transconductance arise from other short-channel effects as carrier velocity saturation (mobility reduction due to the longitudinal field), VFMR (vertical field mobility reduction) and DIBL (drain-induced barrier lowering), which all work in the same direction (but with less impact than CLM causes).

You could check these differences by displaying the I_d vs. V_ds characteristics for different channel lengths for your own process.