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Problem in verilog coding of a noise shaping filter

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hamidyadegaramin

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I am designing a noise shaping block as seen here the Simulink file is also attached. I accomplished it in Simulink and want to transfer it to Verilog. However, I faced with very robust miscalculations. The output in Verilog goes unstable . I have no idea how to solve it. If possible could you please your comments and idea about the design?

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Code Verilog - [expand]
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module MSBx (clk, rst, I,FB1,FB2,O,O2);
input  signed[13:0] I;
input  signed[13:0] FB1;
input  signed[14:0] FB2;
output signed [14:0] O;
output signed [14:0] O2;
input rst;
input clk;
wire signed [13:0] FB1;
wire signed [14:0] FB1_;
wire signed [14:0] FB2_;
wire signed [17:0] I2;
wire signed [14:0] FB2;
wire signed [14:0] RFB2;
wire signed [14:0] RFB1;
wire signed [17:0] OINT1;
wire signed [17:0] OINT2 ;
wire signed [17:0] Iinteg_1;
wire signed [17:0] Iinteg_2;
wire signed [14:0] SQO;
wire signed [17:0] SQE;
wire signed [14:0] SQI;
 
//assign RFB1= {OINT2[14:10],10'b0000000000}; 
//assign RFB2= {OINT2[14],OINT2[14:1]};
assign  I2 [17:0]= {{4{I[13]}},I[13:0]};
//assign FB1_ [14:0]= {FB1[13:0],1'b0};
//assign FB2_ [14:0]= {FB2[13],FB2[13:0]};
assign Iinteg_1 = I2-SQOE+OINT1;
assign SQI = OINT2[14:0];
 
assign SQOE={{3{SQO[14]}},SQO[14:0]};
assign Iinteg_2=OINT1+OINT2-SQOE<<<1;
 
assign O=SQO[14:0];
assign O2=OINT1[14:0];
 
INT integ1x(.clk(clk), .rst(rst), .I(Iinteg_1), .O(OINT1));
INT integ2x(.clk(clk), .rst(rst), .I(Iinteg_2), .O(OINT2));
SQ SQx(.clk(clk), .rst(rst), .I(SQI), .O(SQO));
 endmodule
///////////////////////////////////////////
module INT (clk,rst,I,O);
  input clk;
  input rst;
  input [17:0] I;
  output reg signed[17:0] O=0;;
 
 
  always@(posedge clk)
  begin
    O <= I  ;
    
  end
  endmodule
////////////////////////////////////////
  module SQ (clk,rst,I,O);
  input clk;
  input rst;
  input signed [14:0] I;
  output reg signed[14:0] O=0;
   always@(posedge clk)
    begin
     if (O > 15'b010000000000000)
begin    
     O <= 15'b010000000000000;
     end
      
     if(O < 15'b110000000000000)
     begin
     O<= 15'b110000000000000;
     end
if (15'b110000000000000< O < 15'b010000000000000)
begin
     
    O[14:10] <= I [14:10]  ;
     O[9:0] <= 10'b0000000000;
 
        end
        end
 
  endmodule

 
Last edited by a moderator:

Your if statements are wrong, they are done as parallel logic they should be nested. This isn't likely the issue you are having, but it's wrong to code it this way. Also I'm not sure how line 73 if (15'b110000000000000< O < 15'b010000000000000) got thorough a syntax check, you can't compare with two constants like that.

Code:
CONSTANT1 < O && O < CONSTANT2

You do know that you can write your constants in something other than binary, e.g. 15'h6000 or even break up the binary values with '_' to make them easier to read, e.g. 15'b_110_0000_0000_0000
 

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