Simulation model for floating gate

Hello,

I need small help regarding the floating gate device. I am designing a non-volatile memory cell and foundry does not have model for floating gate . So I used the Voltage controlled current source to mimic floating gate. For output characteristics, I already had the measurement of previous fabricated custom made floating gate and I inserted the CSV file link for the measurements in vccs. Now for simulation I have to test the floating gate (vccs in my case) for process variations (PVT). For voltage it is simply the increment of voltage, for temperature I somehow scale the output based on the temperature value. But for process variation, it is not possible to use this vccs . So can anyone guide me is there any way I could mimic floating gate using simple P-MOS transistor of the technology I am using?.

I have found some papers online on simulation model of floating gate:

1. Cadence-based simulation of floating-gate circuits using the EKV model

2. Practical Simulation Model of Floating-Gate MOS
Transistor in Sub 100nm Technologies

3. A SIMULATION MODEL FOR FLOATING-GATE MOS
SYNAPSE TRANSISTORS

Anyone modeled the floating gate using simple p-mos ? or does anyone have better solution for modeling floating gate?

Thanks

P.S: Sorry if the thread is in wrong section.