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Practical exercises for Xilinx FPGA inbuilt features

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garvind25

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Hi there,

I am relatively new to Xilinx FPGAs. While going through its user guide, I came across several inbuilt components in the IC viz. clock buffers, DCM's and Block RAM. I want to try using these resources. So my query is: does anyone know how to use these inbuilt components. I am looking for small practicals to start of with (I read the 3 chapters painstakingly but could not think of any use of these resources :p).. I also searched the net but am confused as to what is what. I will be grateful to anyone who can give me any small practicals to understand these components. (I have spartan 3 XC3S400 and I code in VHDL).

Also, I want to know which is the simplest FPGA in Xilinx family to have inbuilt ADCs and DACs (like inbuilt ADCs ... in uCs). Upto Spartan 3 there are no onchip ADCs and DACs.

Thanks,

Arvind Gupta.
 

clock buffers, DCM's and Block RAM. I want to try using these resources. So my query is: does anyone know how to use these inbuilt components. I am looking for small practicals to start of with (I read the 3 chapters painstakingly but could not think of any use of these resources :p).. I also searched the net but am confused as to what is what.
  • clock buffers are used to distribute a low skew clock to any FF in the device
  • DCMs are used similar to a PLL to produce different clock output frequencies based on an input clock (i.e if you have a 50 MHz clock input you can output a 100 MHz clock, or a 25 MHz clock, etc)
  • Block RAM are used as RAM memory internal to the device, e.g. FIFOs, lookup tables, etc.

Also, I want to know which is the simplest FPGA in Xilinx family to have inbuilt ADCs and DACs (like inbuilt ADCs ... in uCs). Upto Spartan 3 there are no onchip ADCs and DACs.
Only the higher end families have an ADC (xadc) in them for monitoring the die voltages and die temperature. The Spartan family does not have this feature.

Given your questions I'm assuming you don't know much about digital hardware design, so it would probably help if you study that before FPGAs.
 



  • Given your questions I'm assuming you don't know much about digital hardware design, so it would probably help if you study that before FPGAs.


  • OK thanks. Can you pls. list me what to read/ which book to follow in digital electronics then.

    Arvind.
 

This seemed to be popular at one point Digital Design: With an Introduction to the Verilog HDL 5th Edition by M. Morris R. Mano, Michael D. Ciletti but it's ratings have gone down over the years with each new edition.

There is a much more expensive book that seems to have higher review ratings on Amazon: Digital Design with RTL Design, VHDL, and Verilog 2nd Edition by Frank Vahid.

Then there is this one which seems to get good reviews depending on which version you find 10th seems the best: Digital Fundamentals Value Package (includes Experiments for Digital Fundamentals) (10th Edition) 10th Edition by Thomas L. Floyd

I've never read any of these, I have some ancient college text that is a 2nd edition, which I haven't looked at for 30+ years. Given that people learn things differently, these are only suggestions that others have made. For all we know a 2 star rated book might present the information in a way that "clicks" with your learning style.

There was one free book on the subject that was actually not for purchase that was on the authors website, but I can't seem to find it with morass of copyright violating shady websites. It didn't appear to be all that great of a book on the subject, but it was free. If I find it I'll post the website.
 

Well ... I am a VHDL user... so 1st and 2nd options seem to be a little less relevant. I do know some digital electronics. Will check the Floyd book though... reviews on internet dont mean that it will definitely be good . Also do post the name of the free ebook.

Regards,
Arvind Gupta.
 

Found it.

It's called Digital McLogic Design by Bryan J. Mealy & James T. Mealy. You can find a pdf for it on Bryan Mealy's faculty web page, it used to be hosted on the freerangefactory.org site but is no longer there (removed?). There is also a free VHDL book there too.
 

A practical example of these components comes up in trying to get gigabit ethernet working.

Such a system has the following requirements:
1.) each transmitter has a locally generated clock used for transmission.
2.) data is transmitted as a full packet -- no pausing in between valid data.
3.) actual transmission is "media dependent" (eg fiber vs copper) so you use a standard "media independent interface" to a PHY that connects to the actual port.

A typical system might have a 25MHz clock input. (dev boards might have a 50MHz or 200MHz clock input). GMII -- the standard "gigabit media independent interface" has 8b of data @ 125MHz. 125MHz isn't 25MHz, 50MHz, or 200MHz -- the first problem. The DCM has some limited ability to generate clocks from other clocks though, so it makes sense to generate a 125MHz clock from the system clock.

But 125MHz might not really be the clock rate you want to perform calculations at. You might generate multiple clock frequencies. If you choose 250MHz, it becomes easier to transfer data between the two clock domains -- if done correctly the rising edges of the 250MHz clock will align closely to the edges of the 125MHz clock.

This lets you process and send data, but what of receiving data? The locally generated clocks for ethernet come from imperfect sources. They might be 125,003,125 Hz on your device and 124,998,432 Hz on the device you connect to! So now you have a third clock in your design. Not just that, but you need to use this new external clock to get data into your system -- you actually care about things like difference in delay/phase between the arriving clock and the arriving data. But you also only use the clock for getting data into the system. Now you have choices -- you can use the BUFIO/BUFR to to clock the IO and a limited amount of extra logic. You could also use a BUFG. The BUFG has a lot of delay, so you might use a DCM to generate a phase shifted clock (using feedback) to remove the BUFG's delay.

Next you need data to cross between these "plesiosynchronous" clock domains -- the frequencies being almost equal but not quite. The built in fifo's are great for this as they include logic you can use.

Lastly, when you do send data, you need to do so as a burst. It is easy to use a BRAM to buffer up a full packet to ensure you can send it without interruptions.


This shows a practical design -- multiple clocks for different reasons, buffering of data, and getting data between clock domains.
 

Seems to be a nice example..... but are there any sample codes available to try out. I do not know how to use these blocks. Hence would require these sample codes... (and it need not be a gigabit ethernet, it can be any small unrelated, individual practical exercise highlighting the use of these blocks).

Thanks.
Arvind Gupta
 

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