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Modelling of analog I/O Block in Verilog

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NiedeLu

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Hello guys,
I have some problems in modelling some behaviour of an analog I/O block. Applying a signal to the input pad of this block causes the duty cycle at the internal signal (output) to decrease from 50 to 30% at the worst corner. I want to modell this behaviour but don't know what is the best way. Any suggestions on this? (2xassign statement?) I also want to modell the rise and fall times of the signal. I'm no digital expert so any help is very appreciated.

Thx in advance,
Lukas
 

Are you sure you aren't talking about VerilogA, which is not the same as Verilog (A digital hardware description language).

If you are discussing VerilogA you posted this in the wrong section. As this the "Digital Design and Embedded Programming => PLD, SPLD, GAL, CPLD, FPGA Design" section.
 

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