preethi19
Full Member level 5
Hi i am unable to do design optimization in cadence encounter, i am getting an error regarding that the timing library is not included. During design import i add the following files
1) synthesized (.v) file
2) LEF file
3) timing constraint file (.sdc) that got from synopsys.
I do have the timing lib file (.lib) to include for timing constraint. I found some materials online wer they included .lib file for that. Then what is the need for .sdc file which i extracted from synopsys design vision?? Which is the right file to include???
Also could anyone pls tell me wat an MMMC file is. I can see that file is to configure the rc corners and all but wer can i find this file. Is it generated by synopsys or like should i write my own MMMC file but if thats the case i have no clue of how to write. Can anyone pls give an example. Also i am using tsmc 65nm tech. So how can i know the details if the MMMC file is suitable for 65nm tech. Or is an MMMC file general and has no technology related with it. Can anyone pls help!!! Thank you!!!
1) synthesized (.v) file
2) LEF file
3) timing constraint file (.sdc) that got from synopsys.
I do have the timing lib file (.lib) to include for timing constraint. I found some materials online wer they included .lib file for that. Then what is the need for .sdc file which i extracted from synopsys design vision?? Which is the right file to include???
Also could anyone pls tell me wat an MMMC file is. I can see that file is to configure the rc corners and all but wer can i find this file. Is it generated by synopsys or like should i write my own MMMC file but if thats the case i have no clue of how to write. Can anyone pls give an example. Also i am using tsmc 65nm tech. So how can i know the details if the MMMC file is suitable for 65nm tech. Or is an MMMC file general and has no technology related with it. Can anyone pls help!!! Thank you!!!
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