AMSA84
Advanced Member level 2
- Joined
- Aug 24, 2010
- Messages
- 577
- Helped
- 8
- Reputation
- 16
- Reaction score
- 8
- Trophy points
- 1,298
- Location
- Iberian Peninsula
- Activity points
- 6,178
Hi guys,
I have design a CS amplifier using the EE240 method following the example in the slides.
Now the problem are:
- I have selected the Vgs based on the Id vs Vgs, since I have the Id from the Id vs V* plot.
What happens is that the gain was not as it was supposed to be. So what I did was sweep the Vgs.
Now the problem is that for the value of Vgs that I found, the output is 1.5V which is basically my VDD supply.
If I lower the Vgs I will lose some gain, but I can manage to get the Vo around VDD/2.
The gain goes from 32.3dB with 738mV at the output (and 648mV @ gate) vs 38.5dB with 1.5V at the output.
Can someone give his/her opinion on this? Should I stick with the second option?
I have design a CS amplifier using the EE240 method following the example in the slides.
Now the problem are:
- I have selected the Vgs based on the Id vs Vgs, since I have the Id from the Id vs V* plot.
What happens is that the gain was not as it was supposed to be. So what I did was sweep the Vgs.
Now the problem is that for the value of Vgs that I found, the output is 1.5V which is basically my VDD supply.
If I lower the Vgs I will lose some gain, but I can manage to get the Vo around VDD/2.
The gain goes from 32.3dB with 738mV at the output (and 648mV @ gate) vs 38.5dB with 1.5V at the output.
Can someone give his/her opinion on this? Should I stick with the second option?
