timing constraint- output delay

Hi i am learning Static Timing analysis in vivado. I am working on a simple D-flip flop with 2 inputs (CLK and D) and 2 outputs (Q and Qbar). So i have given delay to the input D of 3ns and i can see that the input is delayed by 3ns (meaning say if the data is to arrive at 5ns then it arrives at 8ns ie 5+3=8ns)...But for output delay i have given 3ns delay. The output slack calculation is done by "Required time - Arrival time". So say my data is required to be present at 15ns and the arrival time is 10ns. I thought then if the arriving time is 10ns then with delay of 3ns sec i would get the data to arrive at 13ns (which is still within the required time). But when i checked the analysis done in vivado i can see the output delay is getting subtracted from the required time ie (15-3=12)... I have written rough numbers here. I have attached an image which would be more clear.

Can someone pls explain this concept..

SDC specifies timing based on external requirements.

Output delay is the trace delay + the setup time required for the external device's setup time. Hence it is subtracted from the clock period.

Input delay is the Tco + trace delay of the external device driving an input. Hence it is added to the data path delay reducing the available time in the FPGA for input setup.

Thank you for the reply!!! So say for instance der is no output delay set then the the "required time" will be around 15ns. So does this mean that the arriving data can arrive anytime within the 15ns. So if we give an output delay so then the "required time" is reduced constraining the output to arrive sooner (like say within 11ns) or else der will be a violation. Am i right??? Its still a bit confusing...

From the point of view of the FPGA timing:

FPGA Tco = Tclock_period - Toutput_delay_value

FPGA Tsu = Tclock_period - Tinput_delay_value


If you don't set an output delay for an output, then any Tco for the FPGA is valid. 0 ns is okay and 50 ns would be okay too.