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[SOLVED] Design Rule Error in Proteus Ares

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mmaher22

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Hello,

I have 2 simillar DRC Errors in Proteus Ares for two capacitors in my PCB the Error is

  • Violation type : "Pad-Pad"
  • Layer: Top
  • Actual Clearance: 9.56th
  • spec'd Clearance: 20th
  • Design Rule: Default

What is the meaning of this error and how it can be solved ?

Thanks in advance
 

The error is self explanatory: The DRC for pad-to-pad clearance is configured on tool as 20"th" but you drew them just 9.56"th" apart. You must move away the pads from each other.
 

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