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modification of braun multiplier

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braun1234

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hiii...
i need to modify the architecture of braun multiplier..to reduce the delay...pls help me...as soon as possible..i hav attached the basic architecture of braun multiplier...pls look into
 

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There is a weird set of papers about Braun Multipliers in FPGAs. Some of the ideas make sense for ASICs, and apparently can work in certain cases for FPGAs.

The easiest method published was to use a carry-lookahead adder instead of the final ripple carry adder. Or maybe to use the fast carry chain for the final ripple carry adder.

The primary reason I see for braun multipliers in FPGAs is writing articles about braun multipliers in FPGAs. If you aren't writing an article about braun multipliers in FPGAs, try using "x*y" or using the builtin multipliers.
 
There is a weird set of papers about Braun Multipliers in FPGAs. Some of the ideas make sense for ASICs, and apparently can work in certain cases for FPGAs.

The easiest method published was to use a carry-lookahead adder instead of the final ripple carry adder. Or maybe to use the fast carry chain for the final ripple carry adder.

The primary reason I see for braun multipliers in FPGAs is writing articles about braun multipliers in FPGAs. If you aren't writing an article about braun multipliers in FPGAs, try using "x*y" or using the builtin multipliers.


thank u so much...actually on my project and braun multiplier is important part of it...nd replacing the final ripple carry adder with CLA is good...but wat im looking forward is modification at architectural level....if u hav any idea..pls help
 

So is the plan to get someone on edaboard to come up with a novel architecture that you can then publish as your research topic into Braun multipliers?
 

sir/madam
im sry...i guess i was not able to convey my need properly...
wat im looking forward is some HELP...some IDEA..
im new to all the topics...i cam in search of help...
pls dont misunderstand..
 

thank u so much...actually on my project and braun multiplier is important part of it...nd replacing the final ripple carry adder with CLA is good...but wat im looking forward is modification at architectural level....if u hav any idea..pls help

That seems really odd for an FPGA design. My thought would be to look at how they get implemented now and what the problem is.

Using a CLA in an FPGA is almost never better than using the fast carry logic. This is why I wonder if the papers about Braun multipliers manually created a lower performance LUT based ripple carry adder.

You could also try replacing the ripple carry adder with the fast ripple carry adders inferred by just using "a+b".
 
il try it this way thank you....
 

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