how to implement ipfilter on fpga?

I'm going to implement ipfilter on fpga. its firmware is available, but I don't know how I can implement it on fpga?
is it possible to do it?
what's the best method? is there any software which convert C code to verilog code?
thanks.

You need to study up on digital filters. There is a vast amount of information available. The simple answer to your question is that most FPGA vendors provide configurable filter IP. You just plug in your requirements, and you get a drop-in module.

barry said:

You need to study up on digital filters. There is a vast amount of information available. The simple answer to your question is that most FPGA vendors provide configurable filter IP. You just plug in your requirements, and you get a drop-in module.

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thanks for the comment. I didn't understand you. ipfilter is not a digital filter like butterworth, ... . it's a firmware which most of linux operating systems have it. it is used to filter the input packet which received from a net ( firewall). I apologize for my bad english.

You mean an IP filter it's normally not concatenated together as "ipfilter".

There is the RFC which defines how the packet is supposed to be interpreted, it's pretty easy to read each word and extract the information from the IP headers, it just requires an FSM/counter to keep track of the position of the word and hence the contents of that word. The filtering part comes in when you have criteria that defines what you are going to do with the packet after you've examined the header, e.g. forward the packet payload, drop the packet, or whatever you need to do.

I've never seen any generic HDL code for this, I've always just written it myself for the specific application. If it isn't available (for free) on opencores then it's not likely something that will be available for free.

It depends how complex you want the filtering to be, and what the performance requirements and error handling requirements are.

For example, basic filtering can be accomplished as the data arrives and as the packet is being parsed. Other filtering requires a packet buffer and some fpga implementation of an algorithm and data structure.