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Two Dimension memory fpga

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Serwan Bamerni

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Two Dimension memory

Hello everyone

As I know all memory models in FPGA are 1-Dimension array when generated either by logic ip core or manually (self programming), in which each location address is specified by a number like mem(5) that refer to position 6 in the memory model mem.

My question is, it is possible (and legal) to infer a 2-Dimension array to save some intermediate value of an image so each location address is specified for example as mem(4,5)

I know how to generate 2-Dimension array in VHDL but as I said I ask about it is possibility, synthesizability and legality to do that in building an image processing system?
 

Re: Two Dimension memory

In hardware terms there's no difference between a 2-dimensional memory with N x M locations and 1-dimensional memory with P = N*M locations, particularly if N and M are powers of two. Either use log2(N) and log2(M) address lines separately or log2(P) address lines together. Both are synthesizable without restrictions.
 
Re: Two Dimension memory

Thank you for your reply

In this case I need to write my own VHDL code because Logic IP core doesn't support 2-Dimension memory with N x M locations
 

Re: Two Dimension memory

No just use the IP core with the depth == N x M, then access it via:
Code Verilog - [expand]
1

mem[{N, M}]


Code VHDL - [expand]
1

mem(N & M)

N & M should concatenate the N and M values into a single NxM, if the N and M are not powers of 2 then there will be locations that are never accessed.
 
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