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Problem to implement the design

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Jaiko

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Hi,

I have a problem here. I can't implement the design into Basys2 Spartan 3E FPGA Board. It shows warning when I implement it. I don't know how to solve this problem.
 

Jaiko said:
I have a problem here. I can't implement the design into Basys2 Spartan 3E FPGA Board. It shows warning when I implement it. I don't know how to solve this problem.
Click to expand...

Neither do I
 

I tried with this one for .ucf file

try_ucf.PNG

, but it shows this warning

warning.PNG.
 

Did you already try to unfold the warnings? Or just posting useless information for fun?

Is frequency a bit variable? I guess it's a vector and you need to assign a location for every bit. Posting the top level design should clarify.
 

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