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verilog code to find max and min in an input..

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MR.sam

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I want to find max and min in input file, read from a memory. This input file containsize 1000 decimal sample values. I have written the following code to find max and min by comparing with a threshold.

Code Verilog - [expand]
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module max_min(input clk, input [15:0]din, output [15:0]dout);
    reg [15:0]max=0;
    reg [15:0]min=0;
    always @(posedge clk)  begin
        if($signed(din)>max)
            max=din;
        else if($signed(din)<min)
            min=din;
    end
    assign dout=max;`
endmodule

The problem in above code is that for example the if condition becomes true for (eg) the 2nd cycle sample value, then max will be assigned the 2nd sample value as max sample value. Now let us consider that input din has max sample value at the 15th cycle of all the 1000 samples. So after the 15th cycle max will contain that max value and the output dout will contain max value after 15th cycle and before 15th cycle it will contain the maximum of the first 14 sample values. I want my output i.e max register to contain only the maximum value i.e the 15th value.
 
Last edited by a moderator:

Presently your design has only one max register, min register is causing no design output and will be ignored in synthesis.

max is updated each time din is exceeding the previously stored max value. Obviously, the new value can't be known before din arrives. (There's no known Verilog syntax to accomplish a prophecy, I believe)

So how do you want the design to behave differently? You can e.g. have a separate max_final output register that copies the internal max value when the 1000 samples have been processed. Requiring a respective store input.

Side remark, there should be an asynchronous reset or synchronous init input to initialize the min/max registers.
 
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    M

    MR.sam

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FvM said:
Presently your design has only one max register, min register is causing no design output and will be ignored in synthesis.

max is updated each time din is exceeding the previously stored max value. Obviously, the new value can't be known before din arrives. (There's no known Verilog syntax to accomplish a prophecy, I believe)

So how do you want the design to behave differently? You can e.g. have a separate max_final output register that copies the internal max value when the 1000 samples have been processed. Requiring a respective store input.

Side remark, there should be an asynchronous reset or synchronous init input to initialize the min/max registers.
Click to expand...

thanks for yours reply..dear i want that my max reg contain only the maximum value among all 1000 sample values..can u suggest me some modification in this code?

- - - Updated - - -

MR.sam said:
thanks for yours reply..dear i want that my max reg contain only the maximum value among all 1000 sample values..can u suggest me some modification in this code?
Click to expand...

hi FvM..thaks alot for yours reply..dear i want to find a single max and min value in input din, so further i can normalize my input signal din by following formula..
din_n=din-min/max-min;
 

i want to find a single max and min value in input din, so further i can normalize my input signal din by following formula..
din_n=din-min/max-min;
Click to expand...

There are essentially two options to know min and max beforehand.

- read the file twice. Determine min and max in first pass and perform normalization in second pass
- read all data into a memory array
 

FvM said:
There are essentially two options to know min and max beforehand.

- read the file twice. Determine min and max in first pass and perform normalization in second pass
- read all data into a memory array
Click to expand...

i have written the complete code as follows for normalization but it didn't give the result which i expect
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module max_min(input clk, input [15:0]din, output [15:0]dout);
reg [15:0]max=0;
reg [15:0]min=0;
reg [15:0]din1;
reg [15:0]din2;
always @(posedge clk) begin
if($signed(din)>max)
max=din;
else if($signed(din)<min)
min=din;
end
always @(posedge clk) begin
if(rst)
din1<=0;
din2<=0;
else
din1<=(din-min);
din2<=din1>>(max-min);
end
 
assign dout=din2;
endmodule..

plzz help me out by suggesting correcting this code..
 
Last edited by a moderator:

You don't have a memory array, so I presume you want to read the file twice.

Code: 
din2<=din1>>(max-min);
I don't see how logical right shift should be related to division respectively normalization.
 

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