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implementing Mixed signal design in FPGA

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abdoo

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Hi all,

I'm trying to implement a Mixed signal system in an FPGA it consist of:

-guassian generation module in verilog (16 bit outputs) coded in SV
-Low pass filter (input/output are real typed) = coded in SV
-SDM modulator (input real, output is bits)=coded in SV


the problem is that in FPGA we cannot implement blocks with real numbers, and conversion function in SystemVerilog are not synthetizable. so what could be the solution?
 

if you want to use floating point, you need to use logic arrays and floating point cores, versions of which are provided by the chip manufacturers.
 

95 to 99 percent of mixed signal designs (digital processing of analog signals) are coded using fixed point numbers. Common digital audio or video systems are using it, too. As said, real isn't synthesizable, floating point is useful only for a very limited application range. Why do you think to need real numbers?
 

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