[SOLVED] gate and drain high impedance node..

Hi i know gate and drain are considered to be high impedance nodes except when the transistor is diode connected then drain has reduced imp. I understand gate being a high imp node.
1) But how is drain a high impedance node (if not diode connected). My understand of high impedance is it resists the flow of current and something of high impedance would have high resistance of current. But when VDS is applied current actually flows through the drain to the source. I understand the channel between drain and source is like a resistor and would resist some flow of current. Is this wat they refer to high impedance or is there any other logic behind this???

2) How is the drain impedance reduced when diode connected??? Pls help!!!

In penthode region of operation (simply saturation) channel cross-section is a triangle tapering close to drain region. In an ideal mosfet channel never achieve drain region. The carriers are transported to the drain through the diffusion only (with some additional assumptions). Its reflect with a flat output characteristic of mosfet. It is a reason of high impedance seen from drain.

//edit:
About second question.
It could be explained in two similar ways:
1. from signal point of, mosfet is a voltage controlled current source. By diode connection we make it as current source controlled by voltage on itself. This kind of vccs is a simply resistor with resistance equal to inverse of transconductance rout=1/gm. More completely we driving mosfet with its voltage drop, so we increasing its current with voltage on it (diode behaviour).

2. from feedback point of view. We applying negative feedback (common source amp inverting signal) from output (drain) to the input (gate), so an output resistance is divided by mosfet self gain. So rout = rds/(gm·rds)=1/gm

High impedance doesn't mean the drain can't carry significant current, it means that, in the saturation (active) region the current does not vary much with a change in drain voltage. In that region the current is largely determined by the gate-source voltage.
In other words the drain tends to look like a current source (sink).

Thank you for the reply!!! So does it mean drain in saturation has high impedance allowing less current flow while drain in triode and subthreshold has low impedance????

preethi19 said:

.............. So does it mean drain in saturation has high impedance allowing less current flow while drain in triode and subthreshold has low impedance????

Click to expand...

Very little current flows in the subthreshold region.
A FET can carry high current and exhibits a lower impedance when it is in the linear region.
If the Vgs is sufficiently high then the FET is fully turned on and the current is limited only by the small Rds intrinsic resistance of the FET.