[SOLVED] Difference in Combo Loop & Latch

Hi,

I am confused with the term combo loop & latch.

When will tool suppose to generate a combo loop & when a latch?

For ex:- The code shown below generates the Latch as per
my understanding but few of the techies were not satisfied with
my reply & they said me it's a combo loop:-

assign q = clk ? d : q;

My point is what makes tool with respect to code to generate combo
loop & latch.

Thanks

A combinational circuit with an output that is fed back as one of the circuits inputs is a combo loop. As you've written it with a clock selecting a D input or the feedback path the assignment describes a latch that has a combo loop. Both of which aren't a good idea to implement in an FPGA.

If this was an interview question and the interviewer(s) were giving you a hard time about it...then they where full of themselves jerks.

ads-ee said:

A combinational circuit with an output that is fed back as one of the circuits inputs is a combo loop. As you've written it with a clock selecting a D input or the feedback path the assignment describes a latch that has a combo loop. Both of which aren't a good idea to implement in an FPGA.

If this was an interview question and the interviewer(s) were giving you a hard time about it...then they where full of themselves jerks.

Click to expand...

Hi Ads,

Thanks for you reply. I know both are not good for FPGA/ ASIC design. But I am still confused:-

#1. What if I write "assign q = rst ? d : q;" still it infer Latch with a combo loop inside it. But
this time it has no clock. It doesn't matter the design has clock or not it's the way the logic
gets implemented.

#2. You said "it describe a Latch that has a combo loop". But that's how a Latch is. Even a flop
internal circuit has a loop. Does that means they are not correct circuits? A Latch is
Latch because its a loop but probably its not correct to say it a combo loop.

#3. Then what exactly is a combo loop. It would be helpful if you can give some simple example
which differentiate a Latch and a combo loop.

Thanks

combinatorial loops may or may not have memory. They may or may not be stable.

An example of a combinatorial loop that doesn't have memory but is stable is a one's complement adder. In this circuit, the final full-adder's carry out is used for the first full-adder's carry in. All inputs result in unique outputs despite this. Note that there are implementations that use two adder circuits and a mux to avoid this. A ones-complement adder _can_ be implemented as a combinatorial loop, but does not need to be implemented as a combinatorial loop.

An example of a combinatorial loop that doesn't have memory and isn't stable is a ring oscillator. This circuit only makes sense when gate delays are taken into account.

An example of a combinatorial loop that has memory is a latch.

This means that some combinatorial loops are not latches, and that some are not stable.



latches are rarely intentionally used in FPGA/ASIC designs at this time. Knowledge of latches and design with latches is primarily used to know why they are not preferred, and to work with external components that have latch-like interfaces.

Combinatorial loops that are not latches are even more rare.

Developers attempt to remove both latches and combinatorial loops as they are almost always a sign of a coding mistake.

Hi,

Thanks for your reply.

So lets conclude. Please correct me if I am wrong.

There are two types of combo loop & they are further sub-divided in two class:-

a) Memory based Combo Loop
a.1) Stable
a.2) Unstable

b) Memory Less Combo Loop
b.1) Stable
b.2) Unstable

Acceptable combo Loop:-
Means a combo loop is purposely in the circuit for its functional behavior and doesn't
cause an output to go unstable.
For Ex:- a) Memory based Combo Loop
a.1) Stable : Latch's (Of-course depend upon the type of Latch)
b) Memory Less Combo Loop
b.1) Stable : 1's Complement Adder

Unacceptable combo Loop:-
Means a combo loop which is generated in the circuit by mistake and causes an output to go unstable.
For Ex:- a) Memory based Combo Loop
a.1) Unstable : I have no idea ???? **
b) Memory Less Combo Loop
b.1) Unstable : Ring Oscillator

So, if we see an actual combo loops are the one which are memory less & creates an
unstable outputs (Dangerous for any implementation).

**Next, a Memory based Unstable combo loop, I don't know any example so can't comment.
Please let me know if there is anything like this.

The remaining are the combo loop for the circuit functionality & may not be dangerous
till outputs are stable.

Please correct me if I am wrong & please provide an input for ** marked point.

Well, "acceptable" is what will get you in trouble in interviews.

Latches are rarely used. I've used maybe one or two intentionally over the last decade. Likewise combinatorial loops like the 1's complement adder are rarely used. The adder was the only example I know of to justify a combinatorial loop, and even then it is more common to use alternative implementations anyway. Ring oscillators are more of an analog design construct and less of an RTL construct.

Hi,

Thanks for your time & explanation.

So, I think it's depend on how one can put it across.

Regarding Unstable Memory based combo loop I think JK latch
is a good example for "11" input.

Thanks