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What is incremental delay on "instance arc"?

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evesjh77

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Hi.

Now I am doing pnr some asic chip by using cadence tool(Innovus).
It is 10nm process and using AOCV.
Anyway, my question is..
After Routing stage, incremental delay(delta delay) is appeared both net and cell.
I know that incr delay is made by crosstalk.
So I thought that it is added to net delay.
But in the timing reports, incr delay exist on cell delay and it is bigger then net incr delay which is connected to the cell.
So , How can I understand that?
Please some one tell me about that.

(I'm not good at English,so please consider about it.)
 

Standard cells have routing in them. This routing is not crosstalk free.
 

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