How FPGA (especially xilinx virtex7) makes use of LUTs and Flipflops internally ?

In terms of design logic, i heard somewhere that any logic without a feedback path (i.e combinational) fits into the LUTS. and sequential logic or control path design sits inside flipflops.

am i correct, please correct me

Logic signal path can usually be conceptualized like this input -> register -> combinatorial logic -> register -> combinatorial logic -> register -> ... register -> output. Basically a chain or registers with combinatorial logic in between. The combinatorial logic may be fed by multiple registers and output into a single register and vice versa.

Programmable logic devices usually consist of something called a logic block which consists of a LUT table containing combinatorial logic gates along with atleast one register. When design is to be fitted into the FPGA, a post fit netlist is created which describes how our desig maps to these logic blocks. Note that Altera and Xilinx use slightly different terminology to describe basically the same thing be it logic block, adaptive logic module, logic element e.t.c. Fundamentally if it has a look up table combined with atleast one register, that is what matters.

A sequentual circuit would usually consist of registers and combinatorial logic. But lets take example of a shift register which has no combinatorial logic. It can be implemented using the logic elements i.e use the register from multiple logic block, route them together in a chain to create a shift register and not use the look up table part of any logic block. Depending on the specific nature of the logic block for a given device, if has only 1 entry into the logic block, it means that the look up table part cannot be used at all and is wasted since that one entry into the logic block has been connected directly to the register, completely by-passing the look up table. If there are two entries and two exits then perhaps the look up table can still be used seperately from the register. No need to say anymore since this aspect of logic block is device and manufacturer specific.

A combinatorial function is implemented using the look up table part since that that is where the logic gates are in a logic element.

Caution: FPGA designs do not like feedback paths that do not have a clocked register in it i.e purely combinatorial feedback path. This creates problems in timing analysis and can lead to a situation where logic level does not settle due to the continuos feedback which may have serious ramifications.

I do not understand why you bring feedback path into this. The bottom line is that the combinatorial part of design uses the look up table. When a signal is to be stored in a register e.g at a clock edge event, then the registers are used.

FPGA logic blocks are comprised of LUTs and registers. Combinational logic uses only LUT and bypasses registers, sequential logic uses both.