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floating gate TSMC 40nm PO.R.8

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MSLayout

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Hi,

We are experiencing a drc error on one gate of a test chip. The signal goes to a MOM cap and a pimplant resistor chain and no where else.
This gate signal is now being flagged as a floating gate with the drc error as

PO.R.8 { @ It is prohibited for Floating Gate if the effective source/drain is not connected together
Float_GATE_fail_n NOT INSIDE SRAM_REGION
Float_GATE_fail_p NOT INSIDE SRAM_REGION
}


The layout is drc (without full chip on) and lvs clean. Any help would be appreciated.
 

Maybe this floating gate error is a chip level DRC and not enabled in the local DRC you're running. In any kit, when you run DRC on circuit level (not chip level), not all the DRC rules are enabled, for instance, the metal intensities, or the via arrays DFMs are not enabled, and the drc check does not report errors though they exist. So if this is the issue, then your drc without the full chip on was not clean, this PO.R.8 error was just not checked. Read your kit drc manual about the PO.R.8 to ensure you understand the issue.
 

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