[SOLVED] simulation stops after 1 clock

214 · Apr 29, 2016

Code VHDL - [expand]
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LIBRARY IEEE;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
 
ENTITY dwt IS
  PORT
  (
     clk : IN STD_LOGIC;
     vid_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0);   -- Pixels from main memory
     hor_sync: IN STD_LOGIC;                    -- Horizondal synchronous pulse
      vert_sync: IN STD_LOGIC;                   -- Vertical synchronous pulse
      val_flag: IN BIT;                          -- Flag indicates valid pixels 
      vid_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      v_out: OUT STD_LOGIC;
      h_out: OUT STD_LOGIC;
      val_out: OUT STD_LOGIC
  ); 
END dwt;
  
ARCHITECTURE dwt_behaviour OF dwt IS
  TYPE buf_ary IS ARRAY(NATURAL RANGE <>) OF UNSIGNED (8 DOWNTO 0);
TYPE buf_ary_1 IS ARRAY(NATURAL RANGE <>) OF SIGNED(7 DOWNTO 0);
TYPE buf_ary_dd IS ARRAY(NATURAL RANGE <>) OF sfixed (3 DOWNTO -3);
TYPE buf_ary_d IS  ARRAY (NATURAL RANGE <>) OF sfixed (4 DOWNTO -9);
   --Internal Buffers 
  SIGNAL buffr: buf_ary_1(99 DOWNTO 0 ):=(OTHERS=>(OTHERS=>'0')); -- Internal Buffer into which pixels will be loaded
  SIGNAL buffo: buf_ary (99 DOWNTO 0 ); -- Internal Buffer into which pixels will be stored
  SIGNAL d : buf_ary_dd (102 DOWNTO 0):=(OTHERS=>(OTHERS=>'0'));
SIGNAL dd : buf_ary_d (102 DOWNTO 0):=(OTHERS=>(OTHERS=>'0'));
  SIGNAL data_in: STD_LOGIC_VECTOR(7 downto 0);
   SIGNAL shift   : BIT:='0';                       --Control signal to manage the row caches    
   SIGNAL flush_pip:BIT:='0';                  --Control signal to omit first and last column
  SIGNAL ready : BOOLEAN:=FALSE;  -- Controll signal to manage output of the system
SIGNAL temp1: sfixed (3 downto -3);
SIGNAL temp: sfixed (3 downto -3) ;
SIGNAL i : integer := 0;
SIGNAL s : buf_ary (102 DOWNTO 0):=(OTHERS=>(OTHERS=>'0'));
signal temp2 : sfixed(4 downto -9);
SIGNAL row : buf_ary_1(2 DOWNTO 0); --row Cache
SIGNAL res_row : SIGNED(7 DOWNTO 0);      
--SIGNAL res_row  : buf_ary(3 DOWNTO 0); --Result row Cache
 --Status signals
  SIGNAL col_res : INTEGER; -- Total columns
  SIGNAL row_res: INTEGER; -- Total Rows
SIGNAL fin:BIT:='0'; --Internal status signal showing end of  frame
 
signal b : sfixed(0 downto -6);
  signal sgn : signed(7 downto 0); 
 
BEGIN
  --************************* Represents the buffering of incoming frame in DDR3 Memory (transfers pixels from vid_in to buffr)*****
  buff : PROCESS(clk)             
   VARIABLE index: INTEGER :=0;
   VARIABLE row_cnt: INTEGER:=0;
   VARIABLE col_cnt: INTEGER:=0;
   VARIABLE col_tr: BOOLEAN:=FALSE;
  BEGIN
      IF CLK'EVENT AND (CLK='1') THEN
          IF (val_flag='1') THEN 
 
 
                  --buffr(index)<=('0' & UNSIGNED(vid_in));             --transfers pixels from vid_in to buffr
                        sgn <= signed(vid_in);
                                buffr(index)<=(sgn);
                        index:=index+1;
                    IF (col_tr=FALSE) THEN
                        col_cnt:=col_cnt+1;
                             END IF;
         END IF;
--If horizontal synchronous pulse is 1, it is the end of the row          
        IF (hor_sync='1') THEN
            row_cnt:=row_cnt+1;
                    IF (col_tr=FALSE) THEN
                        col_res<=col_cnt;
                        col_tr:=TRUE;
                    END IF;
        END IF;
--If vertical synchronous pulse is 1, it is the end of the column       
        IF (vert_sync='1') THEN
             row_res<=row_cnt;
             --row_cnt:=0;
             col_cnt:=0;
             index:=0;
      END IF;
    END IF;   
    END PROCESS buff;
 
dwt_i:PROCESS(clk)
VARIABLE j : integer := -2;
VARIABLE i1 : integer := 2;
VARIABLE i2 : integer := 0;
VARIABLE a : integer := 1;
BEGIN
 IF(clk'EVENT AND clk='1') THEN
    IF ( vert_sync ='1') THEN
 
        row(2 downto 0) <= buffr((i1) downto (i2));
 
        j  :=j+1;
        i1 := i1+2;
        i2 := i2+2;
        i<=j+1;     
        a := a+1 ;
    END IF;
 END IF;
 
 
IF(clk'EVENT AND clk='1') THEN
 
IF a /= 4 THEN
temp1<= to_sfixed( (row(1)-((row(0) + row(2)) srl 1)) );
        ELSE
            temp1 <= to_sfixed (row(1) - row(0));
            a := 0;
        END IF;
 
END IF;
 END PROCESS dwt_i; 
 
 
d_assign: PROCESS(temp1)
    begin
    b <= to_sfixed (0.703125,b);
    
    temp2 <= temp1 * b;
    
d(i)<= (temp1(3)&temp1(2)&temp1(1)&temp1(0)&temp1(-1)&temp1(-2)&temp1(-3));
 
dd(i)<= (temp2(4)&temp2(3)&temp2(2)&temp2(1)&temp2(0)&temp2(-1)&temp2(-2)&temp2(-3)&temp2(-4)&temp2(-5)&temp2(-6)&temp2(-7)&temp2(-8)&temp2(-9));
 
END PROCESS d_assign; 
 
 
END dwt_behaviour;

the code doesnot show any error but the simulation stops after 1 clock...
what is the problem ?
thanks in advance

TrickyDicky · Apr 29, 2016

Did you run the simulation only for a single clock?

you only posted the design, not the testbench

214 · Apr 29, 2016

the test bench is as follows:

Code VHDL - [expand]
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--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.ALL; 
USE work.edge_package.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY camera IS
  GENERIC( fi_n: STRING :="hexi.dat"   ;  -- Input hex file name
                     tclk: TIME:= 100ns              -- Clock speed
                   );
END camera;
 
ARCHITECTURE behavior OF camera IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT dwt
    PORT(
          clk : IN  STD_LOGIC;
          vid_in : IN  STD_LOGIC_VECTOR(7 downto 0);
              hor_sync: IN STD_LOGIC;
              vert_sync: IN STD_LOGIC;
          val_flag : IN  BIT;
          vid_out : OUT  STD_LOGIC_VECTOR(7 downto 0);
          v_out: OUT STD_LOGIC;
          h_out: OUT STD_LOGIC;
          val_out: OUT STD_LOGIC    
         );
    END COMPONENT;
    
    COMPONENT moniter
      PORT(
         clk_i : IN STD_LOGIC;
         vid : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         v_in : IN STD_LOGIC;
         h_in: IN STD_LOGIC;
         val_in: IN STD_LOGIC;
         sts: OUT STD_LOGIC
          );
    END COMPONENT;         
 
   --Inputs
    FILE image: TEXT OPEN read_mode IS fi_n;   
       SIGNAL clk : STD_LOGIC := '0';
     SIGNAL vid_in : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
       SIGNAL hor_sync: STD_LOGIC:='0';
     SIGNAL vert_sync: STD_LOGIC:='0';  
     SIGNAL val_flag : BIT := '0'; --Data Validation flag
     SIGNAL vid_t: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
     SIGNAL hor_t:STD_LOGIC:='0';
     SIGNAL ver_t:STD_LOGIC:='0';
     SIGNAL val_t:STD_LOGIC:='0';
     SIGNAL finish:STD_LOGIC:='0'; 
     
     --Outputs
    SIGNAL vid_out: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'0');
 
BEGIN
 
  
 
-- Instantiate the Unit Under Test (UUT)
   uut: dwt PORT MAP (
          clk => clk,
          vid_in => vid_in,
             
          hor_sync=>hor_sync,
            vert_sync=>vert_sync,
          val_flag => val_flag,
          vid_out => vid_t,
          v_out=>ver_t,
          h_out=>hor_t,
          val_out=>val_t
          );
  
  --Instantiate display device        
  uut1: moniter PORT MAP(
          clk_i =>  clk,
          vid => vid_t,
          v_in => ver_t,
          h_in => hor_t,
          val_in => val_t,
          sts => finish
        );
          
   -- Stimulus process
   stim_proc: PROCESS
     VARIABLE chr: CHARACTER;
     VARIABLE buf: LINE;
     VARIABLE good: BOOLEAN:=FALSE;
     VARIABLE vid_tmp: STD_LOGIC_VECTOR(7 DOWNTO 0);
     VARIABLE tmp: STD_LOGIC_VECTOR(3 DOWNTO 0);
     
   BEGIN        
        IF NOT(ENDFILE(IMAGE)) THEN
          READLINE(image,buf);               ---Read Hex image file to buffer
          FOR i IN buf'RANGE LOOP
            READ(buf,chr,good);               ---Character read from the buffer 
            IF (good=FALSE) THEN
              EXIT;
            END IF;  
            IF(chr=',' ) THEN
               val_flag<='0';
              hor_sync<='1';
              vert_sync<='0';
              ELSIF(chr='*') THEN
                val_flag<='0';
                vert_sync<='1';
                hor_sync<='0';                
            ELSE
             hor_sync<='0';
             vert_sync<='0';
              val_flag<='1';
             stdlogic_conv(chr,tmp); --Procedure to convert hexadecimal string to std_logic_vector
             vid_tmp(7 DOWNTO 4):=tmp;
             READ(buf,chr,good);
                 IF (good=TRUE) THEN
                    stdlogic_conv(chr,tmp);
                     vid_tmp(3 DOWNTO 0):=tmp;
                 END IF; 
            END IF;
            vid_in<=vid_tmp;
             
            WAIT UNTIL RISING_EDGE(clk);
            END LOOP; 
      ELSIF (vert_sync='1') THEN
        
        --If the output file is written, abort the simulation
        --IF(finish='1') THEN
          --        ASSERT (FALSE) REPORT "Simulation failed!" SEVERITY FAILURE;
        --END IF;
        
        WAIT UNTIL RISING_EDGE(clk);  
     END IF ;             
    END PROCESS stim_proc;
     ASSERT (finish/='1') REPORT "One Frame Completed!" SEVERITY WARNING;
   clk <= NOT clk AFTER tclk; -- Clock generation
END ;

TrickyDicky · Apr 29, 2016

how long did you run the simulation for?

214 · Apr 29, 2016

for 31700 ns...timeperiod is 100ns

TrickyDicky · Apr 29, 2016

Please post all of the code (edge_package), monitor entity and the hexi.dat file

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[SOLVED] simulation stops after 1 clock

214

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TrickyDicky

Advanced Member level 7

214

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TrickyDicky

Advanced Member level 7

214

214

Junior Member level 2

TrickyDicky

Advanced Member level 7

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