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connect high frequency ADC (for example FMC160) to a FPGA

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Mansoor1364

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Hi
I have a question about connect high frequency ADC(same FMC160) to a FPGA ,
Max clk frequency is 500MHz but ADC frequency sapmling is 3.6GHz
how manage DATA of ADC in FPGA,
how read data in FPGA?
 

High rate ADCs designed to connect to an FPGA will typically send data with multiple samples per cycle.

For example, 3.6Gsps @ 8b is a little less than 32Gbps. This could be done using 4 10Gbps lanes, or 32 1Gbps lanes. In the FPGA fabric, this might be 9 8b samples per 500MHz cycle, or 18 8b samples per 250MHz cycle.

As a result, FIR filters, mixers, decimators, and slow-control loops make sense at these high rates. Things like IIR filters are much more difficult.
 
Thanks for your explain
under this condition if user needs high frequency clock in FPGA for some processing(same calculate FFT from signal) what is solution by no loss data?
assume:
ADC clk:2 GHz and 16 bit
FFT block:500 MHz and 256 poin

is it right save data in 4, 256 cell RAMs and calculate FFT from this 4 RAM and Simultaneous save data in 4 another RAMs after finish FFT switch to 4 other RAMs?
 

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