Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Pipelined Radix-2 DIF FFT SDF Architecture

Status
Not open for further replies.
M

MjWasHere

Newbie level 2
Joined
Aug 2, 2011
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,300
I want to implement Radix-2 Single-path Delay Feedback (SDF) Decimation-In-Frequency FFT with Pipelining in VHDL and I am trying to understand the below architecture as described in this MIT OpenCourseWare Lecture

radix2_sdf.png

Since its a DIF FFT, shouldn't the upper half of the data be directly passed on to the next stage without requiring multiplication with twiddle factor? Is there a multiplexer which controls multiplication and not shown in the diagram? Can anyone please elaborate on this architecture or provide other references which would help understand SDF better?
 
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top