How to readback an address from FPGA to PC?

Hello,

I am wondering whether the possibility of readback a specific address (for example 0000,000) from FPGA to the PC? Notice that the first for digits are Frame Address and the rest three digits are the bit address.

I think to its possibility via UART interface, but I am not sure about it. Kind helps are cordially appreciated.


Thanks and Regards,

Yes, UART would be a simple way.
Remember that you have to send the address serially and then get back the data serially (bigger the h/w register, more will be the time taken).

msdarvishi said:

I am wondering whether the possibility of readback a specific address (for example 0000,000) from FPGA to the PC?

Click to expand...

Yes

Notice that the first for digits are Frame Address and the rest three digits are the bit address.

Click to expand...

Good thing you pointed it out, I hadn't noticed. It just looked like a bunch of zeros with a comma.

I think to its possibility via UART interface, but I am not sure about it. Kind helps are cordially appreciated.

Click to expand...

UART can be implemented in an FPGA.

Kevin

Even simpler (if you are using Vivado and 7 series or ultrascale parts) is to just instantiate the JTAG-to-AXI4 master. Then all you use are Tcl commands from a Vivado shell to write/read addresses on the AXI bus.

dpaul said:

Yes, UART would be a simple way.
Remember that you have to send the address serially and then get back the data serially (bigger the h/w register, more will be the time taken).

Click to expand...

Thanks @dpaul for your kind reply.
A question please: is it possible to share only 1 urart port for sending address from PC to FPGA and also reading back from FPGA to PC at the same time??

Thanks and Regards,

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ads-ee said:

Even simpler (if you are using Vivado and 7 series or ultrascale parts) is to just instantiate the JTAG-to-AXI4 master. Then all you use are Tcl commands from a Vivado shell to write/read addresses on the AXI bus.

Click to expand...

Thanks @ads-ee for your kind reply,
Indeed, I am using ISE 14.7 targeting a Virtex-5 (XC5VLX50T) FPGA, nor the VIVADO. Is it possible to do so with ISE as well? If so, could you please let me know how to do it with JTAG?

Thanks and Regards,

msdarvishi said:

Indeed, I am using ISE 14.7 targeting a Virtex-5 (XC5VLX50T) FPGA, nor the VIVADO. Is it possible to do so with ISE as well? If so, could you please let me know how to do it with JTAG?

Thanks and Regards,

Click to expand...

You can't there isn't any support in ISE to do this. You're stuck with a custom design or modifying a design, like a UART, you find online somewhere (e.g. Opencores).

Thanks @dpaul for your kind reply.
A question please: is it possible to share only 1 urart port for sending address from PC to FPGA and also reading back from FPGA to PC at the same time??

Click to expand...

I am not familiar with the Virtex-5 (XC5VLX50T) and the development board which contains this part. Also I am using Vivado 2015.4 and it has been years I have not used the ISE suite. So I can only answer your question in a generic way.

Taking the example of the AC701 development board it contains a USB-to-UART Bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS). So I connect my dev board to my PC using the USB cable. Hence I have separate Rx and Tx pins. Using TeraTerm on my PC and a Xilinx UART IP on the dev board, I can easily send and receive signals.
I do this this way only because of my available infrastructure. I am happy with this full-duplex support.

Now in your case you want to use only 1 port for Rx/Tx. While the UART module in your FPGA can be easily modified to use an inout port, I am not sure how this will be handled on the PC side (you have to find this out)!

Secondly sharing only 1 port will enable half-duplex operation. This will slow your communication.

Hope this helps.

dpaul said:

I am not familiar with the Virtex-5 (XC5VLX50T) and the development board which contains this part. Also I am using Vivado 2015.4 and it has been years I have not used the ISE suite. So I can only answer your question in a generic way.

Taking the example of the AC701 development board it contains a USB-to-UART Bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS). So I connect my dev board to my PC using the USB cable. Hence I have separate Rx and Tx pins. Using TeraTerm on my PC and a Xilinx UART IP on the dev board, I can easily send and receive signals.
I do this this way only because of my available infrastructure. I am happy with this full-duplex support.

Now in your case you want to use only 1 port for Rx/Tx. While the UART module in your FPGA can be easily modified to use an inout port, I am not sure how this will be handled on the PC side (you have to find this out)!

Secondly sharing only 1 port will enable half-duplex operation. This will slow your communication.

Hope this helps.

Click to expand...

Thank you @dpaul for your kind reply.

About TeraTerm that you have mentioned, is it a terminal like hyperterminal for Serial communication?? May I use hyperterminal instead?

Yes, I agree with you, sharing a UART port for Rx-Tx will slow the communication speed. I will try to figure it out practically.

Regards,

msdarvishi said:

About TeraTerm that you have mentioned, is it a terminal like hyperterminal for Serial communication?? May I use hyperterminal instead?

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Teraterm is an open source terminal program, hyperterminal will work just fine.[/QUOTE]

ads-ee said:

Teraterm is an open source terminal program, hyperterminal will work just fine.

Click to expand...

[/QUOTE]


Dear @ads-ee, and @dpaul

in order to readback an address from FPGA to PC, how should I instantiate it? in VHDL code? or elsewhere? So, where this read address with be shown? in hyperterminal? Sorry, but ita practice is not mature in my mind. I cordially appreciate if you could help me by that.

Regards,

A UART is just a physical interface to transfer bytes, the concept of address and data will have to be a protocol you design on top of the physical UART layer.

It would be whole lot easier to just use some pre-built canned solution from the vendor for something like a USB-UART or some such and any software that may be pre-written as opposed to using hyperterminal/teraterm and developing your own protocol.

It might be better to tell us what you are trying to accomplish. It may be you've got this idea of addressing the FPGA from a PC and it really is a bad way to approach the design.

ads-ee said:

A UART is just a physical interface to transfer bytes, the concept of address and data will have to be a protocol you design on top of the physical UART layer.

It would be whole lot easier to just use some pre-built canned solution from the vendor for something like a USB-UART or some such and any software that may be pre-written as opposed to using hyperterminal/teraterm and developing your own protocol.

It might be better to tell us what you are trying to accomplish. It may be you've got this idea of addressing the FPGA from a PC and it really is a bad way to approach the design.

Click to expand...

Indeed, I am using the SEU controller macro to inject SEU into the FPGA. So, firstly, define an address as an injection place, then I would like to readback the content of this address to make sure that the content of address have been changed due to SEU injection. The SEU injection is done via UART and now I am working to readback that address to my PC.

So, by this explanation, can you please let me know what to do?

Regards,

msdarvishi said:

Indeed, I am using the SEU controller macro to inject SEU into the FPGA. So, firstly, define an address as an injection place, then I would like to readback the content of this address to make sure that the content of address have been changed due to SEU injection. The SEU injection is done via UART and now I am working to readback that address to my PC.

So, by this explanation, can you please let me know what to do?

Regards,

Click to expand...

Whoa, from you're very first post I was wondering if what you really wanted to do was access the FPGA configuration memory. If you had stated that explicitly from the start, you could have saved both yourself and others time.

So you already have the SEM controller in the design and now want to read the frame from the FPGA? I'm assuming you've read the configuration documents and understand all the commands you have to send to read a frame? You're going to have to add logic to the SEM if you want to read a frame from the ICAP as the SEM uses the ICAP exclusively. If the core is encrypted you might some difficulty with that. The other option is to use JTAG and a JTAG svf player to send the frame reading commands, this avoids the problem with adding logic to override the SEM, though you'll likely run into issues where you have to restart the SEM controller as the JTAG will just takeover when it needs to (that might interrupt a command sequence of the SEM).

If you want to keep it all internal to the FPGA then you should probably look for the document on Xilinx's website that discusses sharing the ICAP with the SEM, I don't remember the XAPP number, but even though it's written for a specific device family the gist of the document is applicable to more than that specific family. If I recall correctly it goes into the requirements of disconnecting the SEM from the ICAP so you can do something else like partial reconfiguration with it.