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Error in Cadence Virtuoso DRC

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P

Pavlanto

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I am running a simple DRC check in Cadence virtuoso.My error is PP.EN1:{NP OR PP} enclosure of PO (except of PO) >=0.15um.
I am running a simple NAND circuit with one Pmos and one Nmos transistor.I use a via to connect the input(metal 1) with the gates(poly).
 

Yes? So?

Have you read the design rules document? It should be
clear about the meaning and logic of the rule. And the
marker should show you the location of what's missing.

I'll leave aside the improbability of making a NAND gate
with only one of each transistor, or the difference
between contact and via.
 

You are right.I designed a NOT gate,thats why i used only 2 transistors.I had a try with a NAND and had the same problem.Of course i know the exact place of the error.It is between the via and the poly.

Here are 3 photos with the circuit,the vias settings and the error

Pav_1.jpg

Pav_2.jpg

Pav_3.jpg
 

If I had to guess further I'd think this is a poly-must-be-doped
rule, and that perhaps (as at many foundries) the field poly is
doped by some Boolean rather than hand drawing P+ or N+ on
all of your local interconnect.

Often this is dependent on some feature like "bulk" which has
to surround the circuit but is not a masking layer. Take a
look at any library cells that may exist for features you
don't recognize / understand.

I still recommend that you read the design rules pertaining
to the error. Add to this the section on mask booleans and
parsing the DRC rule for its logical terms, which should be
directly illuminating.
 

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