Square wave generator with adjustable duty cycle

Hi,
I want to build a circuit generating 40kHz square wave signal with a pulse width of 10x ns i.e. 50ns.
For the 40kHz part, i can do it with a simple 555 circuit but as far as i read, i cannot generate a pulse width as small as 10ns with a 555. I'm not really good at programming a chip so i want to find an analog solution.

I found this topic quite helpful but the final reply of the topic founder did not include the picture of the circuit.
https://www.edaboard.com/threads/182626/

Can anyone help me pls,
Thanks.

You would probably want a 100MHz or *N higher clock, to get a neat
10nS "tick". This will be challenging in SSI logic but doable in a
modern FPGA. Then you need an N=2500 up counter (for the 40kHz)
and a magnitude comparator (a question, can x=0?) where carry
starts the pulse and compare ends it (SRFF?).

2500 is a lot of counter bits and the synchronous logic for it may be
a bit deep and nasty for 100MHz, but I'd stay away from a ripple
design.

Hi,

I agree.
CPLDs are not that complex than FPGAs.
But I'm not sure if you find a CPLD to run a 100MHz 12bit synchronous counter. There may be a timing problem..
The CPLDs I used may be too slow.

But maybe worth to look for one.

Klaus

Hi,
Thanks for all your helps but i'm quite confused.
The real problem is, i have a pair of ultrasonic transducers and i want to build an ultrasonic cleaner with that.
It's a fixed 40kHz transducfer, and the manufacturer also recommend a PCB of their own or the transducers to function;
However, I want to design the PCB on my own for further understanding.
I'm sorry for being annoying but help me, please
Thank you.

Why do you need 10ns pulses for a 40KHz transducer?

dick_freebird said:

You would probably want a 100MHz or *N higher clock, to get a neat
10nS "tick". This will be challenging in SSI logic but doable in a
modern FPGA. Then you need an N=2500 up counter (for the 40kHz)
and a magnitude comparator (a question, can x=0?) where carry
starts the pulse and compare ends it (SRFF?).

2500 is a lot of counter bits and the synchronous logic for it may be
a bit deep and nasty for 100MHz, but I'd stay away from a ripple
design.

Click to expand...

KlausST said:

Hi,

I agree.
CPLDs are not that complex than FPGAs.
But I'm not sure if you find a CPLD to run a 100MHz 12bit synchronous counter. There may be a timing problem..
The CPLDs I used may be too slow.

But maybe worth to look for one.

Klaus

Click to expand...

You could break up the 12-bit counter into three 4-bit synchronous clear enabled counters with TC, then you use the TC of the 1st counter to enable the 2nd counter and both the 1st and 2nd TCs (AND) to enable 3rd counter. To check for the rollover value you create a pipelined test for 3rd (cnt[11:8] == 9) and 2nd (cnt[7:4] == C) the 1st (cnt [3:0]= 3) doesn't need pipelining. The delay due to the pipeline registers for the 3rd and 2nd test don't matter as you'll count from 0-1-2 before reaching 3 on the first counter. The register on the upper nibbles for the compare are there to make sure the timing is met without a large deep combo circuit. Doing this might allow the design to be implemented on a faster family of SSI logic (e.g. using typical values for VHC163), on a CPLD, or on a slower (cheaper) FPGA (e.g. Microsemi, Lattice).

Of course this requires more logic and will require more parts (if using SSI). The key here is to eliminate any deep logic cones and carry chains from the design, by pipelining those key portions of the design.

Personally I think you should just use a CPLD or a small FPGA like Microsemi or Lattice, which will likely be the cheapest simplest solution.

Hi,

.. somthing like this is possible for a fixed value compare like the counter_top: 0x9C3 = 2499,

but it will fail with variable compares like the duty_cycle.
For the duty_cycle compare all 12 counter bits ... pluse the 12 bit compare result ... need to settle before the next rising clock edge.

Especially when the counter_value changes from 0x7FF to 0x800 all 12 bits change.
So a carry_look_ahead or a similar solution is difficult.

Klaus

KlausST said:

Hi,

.. somthing like this is possible for a fixed value compare like the counter_top: 0x9C3 = 2499,

but it will fail with variable compares like the duty_cycle.
For the duty_cycle compare all 12 counter bits ... pluse the 12 bit compare result ... need to settle before the next rising clock edge.

Especially when the counter_value changes from 0x7FF to 0x800 all 12 bits change.
So a carry_look_ahead or a similar solution is difficult.

Klaus

Click to expand...

I wasn't suggesting carry look ahead or similar, the key is pipelining, you pipeline the compares for values before the one you want, then pipeline the comparison results to check if you've reached a specific value.

to check for 0x800 you would..
start with count at 0x7FE and perform the following compares
cmpr_u <= (cnt[11:8] == 7);
cmpr_m <= (cnt[7:4] == F);
cmpr_l <= (cnt[3:0] == E);
1st clock cycle, count changes to 0x7FF and the cmpr_# values get registered
eq_0x800 <= cmpr_u & cmpr_m & cmpr_l;
2nd clock cycle, count is now 0x800 and the eq_0x800 is set.

This only gets messy if you have a requirement to enable disable the counting, which doesn't seem to be the case in this situation as the counter appears to be free running.

I implemented a counter/timer on FPGA using LabVIEW but I cannot provide you the details or the link where to find the info.

BTW, I use a custom board.
I prefer to program the FPGA using LabVIEW instead of VHDL or Verilog, if it is the right choice to you. It is more simple and effective. Time to learn is negligible with respect to VHDL or Verilog.

Cheers,
sirb

I think a key question is whether you (OP) really need such fine
resolution and quantization in the pulse width. If not, a regular
PWM IC and an analog control for duty cycle can make a cleaner
or similar application work just fine. The frewuency is not any kind
of challenge for that sort of part. The minimum on time limit might
be (almost certainly is) a challenge re your 10nS minimum pulse.
But beware overspecifying especially if cost and effort are on you.

OMG,
What are you guys talking about, i dont understand even half of it Sorry.
For further specification, I have a pair of this ultrasonic transducers and this is a recommendedPCB of the manufacturer.
Guys, please help me:
_ What's the input signal of the transducer ( As far as i know, it's a 40kHz square wave signal and my prof said that the pulse width must be really tiny so that it wouldn't damage the transducer, - can you clarify this for me please as he did not tell me why it has to be that way)
_ How can i make the PCB for generating such signal.
Thank you,

The small pulse width stuff is complete nonsense. A power piezo transducer like the device in the link will driven by 40 kHz sine wave, obtained by a matching LC network from a switching stage producing a square wave, e.g. a half bridge circuit. Variable pulse width could be used under circumstances to adjust the power level.

Yes, surely what you need is like an LLC converter circuit, switching at the resonant frequency, designed to be 40khz, , and put the transducer into the 40khz sine wave...and thats it i would have thought.