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LNA layout power less than its schematic

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tm.torabi

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Hi

I have a LNA layout and also the schematic. The layout is LVS free.

The DC power of layout is 17.77m but the schematic is 18.04m.

Is it possible the layout consumes less power than schematic?

Thanks
 

It's only 1.5% less. Relevant tolerances (widths, lengths, also from resistors) are often waved through by the LVS.
Or you have voltage drops in the layout's power supply which aren't considered in schematic.

Actually 18mW seems a bit high for an LNA ... - or does this include several stages?
 
Yes it is possible but at what cost to other parameters?

Review the tolerances of every item parameter to see if it satisfies the design requirements. power vs gain vs efficiency vs distortion.
 
Hi,
Thank you for your reply
It is a differential LNA but it dose not have several stages. If I decrease the current bias I can say it does not have a good performances at all. I tried a lot to find good performances.
Do you have any suggestion for that?
 

Are you talking about the simulated power of schematic-extracted
vs layout-extracted netlists? Or are you talking about somebody
else's annotated numbers?

I have seen some PDKs where schematic netlists have no parasitics
and some where parasitic values are assumed for close-in routing,
and layout extracted will be different than either.

You're only quibbling over a couple of percent and this is way less
than real process scatter in actual silicon is likely to be.
 

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