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`celldefine to reduce RTL simulation time?

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childs

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Hi, I found that my simulation runs faster when I put `celldefine macro in big RTL sub-block or simulation models. Now, says I use `celldefine macro in my RTL sub-block INSTANT_1:

1. I am assuming by using `celldefine macro, the simulation use less memory as it now treats INSTANT_1 as a cell, and does not keep the details inside INSTANT_1 . Is this assumption correct?
2. I am aware that I will not be able to show the waveform of signal inside & of ports of INSTANT_1 after it is treated as a cell. Is there any other impact that I should be aware of?

side note: depending on the size of system I am simulating, this method sometimes reduces really huge amount of simulation runtime, says from 30mins --> 5mins!!

Thanks.
 

The performance you get is very dependent on what you are doing with the block inside your cell. You can get speed up and reduced memory consumption not only from the fact that your are not dumping anything inside the cell, but also from being able to optimize the code inside the cell better because you are not dumping anything inside the cell.

This will also have a huge impact of you are doing code coverage, or any other type of analysis in addition to simulation.
 

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