[SOLVED] LVS check problem - error in lvs check - skill language

Hi all
I am a newer in skill language. I have a new problem. I have been written a code to create a pcell resistor by skill language. The properties of the pcell resistor in schematic and layout are the same. But when I run the LVS check, the mismatch is happened. A reason is that I have changed a function ( the function to calculate resistor value). I changed it in the cdf parameter file, the spice library (to run simulation). I do not know that I must change an other file to pass the LVS check. Have you any ideal for this problem ?

The more immediate question is, "is the extracted value
wrong?". More likely to me is that the new art has some
error in it. Figuring that the foundry has pretty well
verified the extraction deck beforehand.

Properties don't mean a thing, by themselves. It's all
about the uses to which they are put.

If a library resistor of the same species verifies fine,
look to your own code.

Hi dick_freebird,

The extracted value is wrong. Cause that I have changed the function to calculate resistance value. But I run DC simulation and it works (R = V/I, the resistance value from simulation compares with the resistance from my own code are the same). I do not know that I must change the function in other files to the Calibre can "understand" that I have changed function (the function calculate the resistance value).

Thank for your replied.

There are two places that might be setting resistance values on the extracted netlist. The most likely is the DEVICE statement in the SVRF file. I don't think you can modify that with Calibre Interactive, as it is pretty rare you would want to mess with the PDK or your corporate "golden rules". The other place where device properties are sometimes calculated is DFM Property; that is used for more complex devices or derived properties.

The built-in device language is described in the SVRF manual (svrf_ur.pdf) -- it is an entire chapter. The default computations used if a DEVICE statement does not explicitly define the properties are described in the Calibre Verification User's Manual (calbr_ver_user.pdf). (In the 2016 version of the manuals, it is under "Property Computation".) Be aware that if you define one property for a device, none of the default computations for that device type are used; you cannot just override the resistance calculation.

The DFM PROPERTY details are also in the SVRF manual; be sure to scan the description for links to useful examples. It is a pretty complicated statement as it isn't just for device recognition/netlist properties.

Before you go too deep into rewriting the SVRF rules, are you positive your custom resistance calculation is correct? The foundries put a great deal of time into creating and validating the PDK rules so that device properties, parasitics, etc. correctly reflect the real-world effects of their particular manufacturing process. Some of what you might consider to be "missing" might be accounted for in a different section, or "extra" is because at smaller process nodes what used to be insignificant now needs to be included.

Hi slizak,

Your information that are very useful for me.
Thank you so much