Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Parasitic extraction of a metal square in cmos process

Status
Not open for further replies.

vlsi_design2

Member level 1
Joined
Nov 30, 2014
Messages
37
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,562
Hi, I want to find the parasitic of a metal square of given area in a cmos process (tsmc65nm) using regular lvs, xrc flow. But i do not have a schematic for this metal for lvs, xrc.

Some people suggest about using lvsres. But I do not know if it exists for tsmc65nm process. If it exists then what is layout and schematic name for M9?
 

Make a trivial schematic with at least one pin and one
wire. There's your metal schematic. Put the same pin
name on your 1-square layout. See if you can get the
analog extraction to complete with such a trivial case,
you may need to work with pruning of useless nets and
so on.

Or, make a slightly more real layout & schematic with
components connected by this wire. Then dig into the
extracted netlist for the tiny capacitors attached to
that node.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top