Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
For IO testing we do boundary scan also known as JTAG(IEEE 1149.1 standard). This includes EXTEST which test the I/O's as well as the logic between two blocks.
One more method is to use NAND tree test for IO testing which includes the insertion of NAND tree structure at all IO pads on the chip.Then apply your NAND tree pattern and observe the output pattern.
Please correct me if there are more IO tests, other than this.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
